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MLK-16266-02 ARM: imx: Enhance the code to support new TO for imx6qp 

Previous code don't take care about the i.MX6QP revision update of
new TO. So improve the code to include future TO support for i.MX6QP.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
pull/10/head
Bai Ping 2017-08-25 13:22:32 +08:00 committed by Jason Liu
parent 1763bad8b2
commit cdaf92d431
4 changed files with 9 additions and 7 deletions
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4
arch/arm/mach-imx/anatop.c
View File

@ -146,7 +146,7 @@ void imx_anatop_pre_suspend(void)
return;
}
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
imx_anatop_disable_pu(true);
if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||
@ -176,7 +176,7 @@ void imx_anatop_post_resume(void)
return;
}
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
imx_anatop_disable_pu(false);
if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||

2
arch/arm/mach-imx/cpu.c
View File

@ -127,7 +127,7 @@ struct device * __init imx_soc_device_init(void)
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
soc_id = "i.MX6QP";
else
soc_id = "i.MX6Q";

5
arch/arm/mach-imx/mach-imx6q.c
View File

@ -1,6 +1,7 @@
/*
* Copyright 2011-2015 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
* Copyright 2017 NXP.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@ -310,7 +311,7 @@ static inline void imx6q_enet_init(void)
imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp");
imx6q_enet_phy_init();
imx6q_1588_init();
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
imx6q_enet_clk_sel();
}
@ -318,7 +319,7 @@ static void __init imx6q_init_machine(void)
{
struct device *parent;
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
else
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",

5
drivers/clk/imx/clk-imx6q.c
View File

@ -1,6 +1,7 @@
/*
* Copyright (C) 2011-2016 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
* Copyright 2017 NXP.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@ -989,7 +990,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
} else if (clk_on_imx6q()) {
if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL3_PFD0_720M]);
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 720000000);
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
@ -1086,7 +1087,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
* for i.MX6QP with speeding grading set to 1.2GHz,
* VPU should run at 396MHz.
*/
if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
if (clk_on_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) {
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
WARN_ON(!np);