ASoC: au1x: PSC-AC97 bugfixes
This patch fixes the following bugs: - only reprogram bitdepth if it has changed since last call to hw_params. - add locking inside ac97_read/write functions: When reprogramming sample depth, the ac97 unit has to be disabled, which should not be done in the middle of codec register accesses. - retry timed-out codec register accesses. - wait for status bits to set/clear when starting/stopping various functional blocks; very important after reenabling AC97 unit else sound may be distorted (e.g. high-pitch noise in 1kHz sine wave). - clear fifos before/after starting/stopping RX/TX. - longer timeouts waiting for PSC/AC97 ready after cold reset with certain codecs this can take ridiculous amounts of time. Run-tested on various Au1200 platforms with various codecs. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Manuel Lauss
Mark Brown
parent
87831cb660
commit
cdc65fbe18
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@ -1,8 +1,8 @@
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/*
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* Au12x0/Au1550 PSC ALSA ASoC audio support.
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*
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* (c) 2007-2008 MSC Vertriebsges.m.b.H.,
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* Manuel Lauss <mano@roarinelk.homelinux.net>
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* (c) 2007-2009 MSC Vertriebsges.m.b.H.,
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* Manuel Lauss <manuel.lauss@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -19,6 +19,7 @@
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/suspend.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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@ -29,6 +30,9 @@
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#include "psc.h"
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/* how often to retry failed codec register reads/writes */
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#define AC97_RW_RETRIES 5
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#define AC97_DIR \
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(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
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@ -45,6 +49,9 @@
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#define AC97PCR_CLRFIFO(stype) \
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((stype) == PCM_TX ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)
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#define AC97STAT_BUSY(stype) \
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((stype) == PCM_TX ? PSC_AC97STAT_TB : PSC_AC97STAT_RB)
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/* instance data. There can be only one, MacLeod!!!! */
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static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;
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@ -54,24 +61,33 @@ static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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unsigned short data, tmo;
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au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), AC97_CDC(pscdata));
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au_sync();
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tmo = 1000;
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while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)) && --tmo)
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udelay(2);
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if (!tmo)
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data = 0xffff;
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else
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data = au_readl(AC97_CDC(pscdata)) & 0xffff;
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unsigned short data, retry, tmo;
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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return data;
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retry = AC97_RW_RETRIES;
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do {
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mutex_lock(&pscdata->lock);
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au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
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AC97_CDC(pscdata));
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au_sync();
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tmo = 2000;
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while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD))
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&& --tmo)
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udelay(2);
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data = au_readl(AC97_CDC(pscdata)) & 0xffff;
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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mutex_unlock(&pscdata->lock);
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} while (--retry && !tmo);
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return retry ? data : 0xffff;
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}
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/* AC97 controller writes to codec register */
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@ -80,16 +96,29 @@ static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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unsigned int tmo;
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au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), AC97_CDC(pscdata));
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au_sync();
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tmo = 1000;
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while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)) && --tmo)
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au_sync();
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unsigned int tmo, retry;
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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retry = AC97_RW_RETRIES;
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do {
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mutex_lock(&pscdata->lock);
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au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
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AC97_CDC(pscdata));
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au_sync();
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tmo = 2000;
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while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD))
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&& --tmo)
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udelay(2);
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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mutex_unlock(&pscdata->lock);
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} while (--retry && !tmo);
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}
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/* AC97 controller asserts a warm reset */
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@ -129,9 +158,9 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
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au_sync();
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/* wait for PSC to indicate it's ready */
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i = 100000;
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i = 1000;
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while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
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au_sync();
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msleep(1);
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if (i == 0) {
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printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
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@ -143,9 +172,9 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
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au_sync();
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/* wait for AC97 core to become ready */
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i = 100000;
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i = 1000;
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while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
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au_sync();
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msleep(1);
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if (i == 0)
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printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
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}
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@ -165,12 +194,12 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
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{
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/* FIXME */
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struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata;
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unsigned long r, stat;
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unsigned long r, ro, stat;
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int chans, stype = SUBSTREAM_TYPE(substream);
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chans = params_channels(params);
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r = au_readl(AC97_CFG(pscdata));
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r = ro = au_readl(AC97_CFG(pscdata));
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stat = au_readl(AC97_STAT(pscdata));
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/* already active? */
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@ -180,9 +209,6 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
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(pscdata->rate != params_rate(params)))
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return -EINVAL;
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} else {
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/* disable AC97 device controller first */
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au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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/* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
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r &= ~PSC_AC97CFG_LEN_MASK;
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@ -199,14 +225,40 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
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r |= PSC_AC97CFG_RXSLOT_ENA(4);
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}
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/* finally enable the AC97 controller again */
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/* do we need to poke the hardware? */
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if (!(r ^ ro))
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goto out;
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/* ac97 engine is about to be disabled */
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mutex_lock(&pscdata->lock);
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/* disable AC97 device controller first... */
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au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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/* ...wait for it... */
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while (au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)
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asm volatile ("nop");
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/* ...write config... */
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au_writel(r, AC97_CFG(pscdata));
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au_sync();
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/* ...enable the AC97 controller again... */
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au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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/* ...and wait for ready bit */
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while (!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR))
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asm volatile ("nop");
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mutex_unlock(&pscdata->lock);
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pscdata->cfg = r;
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pscdata->rate = params_rate(params);
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}
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out:
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return 0;
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}
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@ -222,6 +274,8 @@ static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
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au_sync();
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au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
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au_sync();
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break;
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@ -229,6 +283,13 @@ static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
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case SNDRV_PCM_TRIGGER_SUSPEND:
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au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
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au_sync();
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while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
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asm volatile ("nop");
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au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
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au_sync();
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break;
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default:
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ret = -EINVAL;
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@ -251,6 +312,8 @@ static int au1xpsc_ac97_probe(struct platform_device *pdev,
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if (!au1xpsc_ac97_workdata)
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return -ENOMEM;
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mutex_init(&au1xpsc_ac97_workdata->lock);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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ret = -ENODEV;
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@ -269,9 +332,9 @@ static int au1xpsc_ac97_probe(struct platform_device *pdev,
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goto out1;
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/* configuration: max dma trigger threshold, enable ac97 */
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au1xpsc_ac97_workdata->cfg = PSC_AC97CFG_RT_FIFO8 |
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PSC_AC97CFG_TT_FIFO8 |
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PSC_AC97CFG_DE_ENABLE;
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au1xpsc_ac97_workdata->cfg = PSC_AC97CFG_RT_FIFO8 |
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PSC_AC97CFG_TT_FIFO8 |
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PSC_AC97CFG_DE_ENABLE;
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/* preserve PSC clock source set up by platform (dev.platform_data
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* is already occupied by soc layer)
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@ -386,4 +449,4 @@ module_exit(au1xpsc_ac97_exit);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
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MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
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MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");
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@ -29,6 +29,7 @@ struct au1xpsc_audio_data {
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unsigned long pm[2];
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struct resource *ioarea;
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struct mutex lock;
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};
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#define PCM_TX 0
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