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drm/radeon/dpm/rs780: add some sanity checking to sclk scaling

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Since the clock scaling is based on fb divider adjustments,
make sure the other pll parameters are the same.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
Alex Deucher 2013-09-13 09:57:50 -04:00
parent c3eaa08827
commit ce7b30e025
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/radeon/rs780_dpm.c
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@ -449,6 +449,12 @@ static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
if (ret)
return ret;
if ((min_dividers.ref_div != max_dividers.ref_div) ||
(min_dividers.post_div != max_dividers.post_div) ||
(max_dividers.ref_div != current_max_dividers.ref_div) ||
(max_dividers.post_div != current_max_dividers.post_div))
return -EINVAL;
rs780_force_fbdiv(rdev, max_dividers.fb_div);
if (max_dividers.fb_div > min_dividers.fb_div) {