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Add a Security SubSystem (SSS) clock for Exynos4, needed by exynos-rng 

driver (Pseudo Random Number Generator).
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Merge tag 'samsung-clk-exynos4-4.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers

Add a Security SubSystem (SSS) clock for Exynos4, needed by exynos-rng
driver (Pseudo Random Number Generator).

* tag 'samsung-clk-exynos4-4.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: exynos4: Add SSS gate clock
steinar/wifi_calib_4_9_kernel
Olof Johansson 2016-01-07 06:05:59 +01:00
parent 326ea45aa8 94af7a3c31
commit ce96cb7386
2 changed files with 2 additions and 0 deletions
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1
drivers/clk/samsung/clk-exynos4.c
View File

@ -1024,6 +1024,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
0, 0),
GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
0, 0),
GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),

1
include/dt-bindings/clock/exynos4.h
View File

@ -93,6 +93,7 @@
#define CLK_SCLK_FIMG2D 177
/* gate clocks */
#define CLK_SSS 255
#define CLK_FIMC0 256
#define CLK_FIMC1 257
#define CLK_FIMC2 258