memstick: optimize setup of JMicron host parameters
Set correct clock management values to improve over-all performance. Signed-off-by: Alex Dubov <oakad@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -131,6 +131,12 @@ struct jmb38x_ms {
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#define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
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#define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
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#define CLOCK_CONTROL_40MHZ 0x00000001
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#define CLOCK_CONTROL_50MHZ 0x00000002
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#define CLOCK_CONTROL_60MHZ 0x00000008
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#define CLOCK_CONTROL_62_5MHZ 0x0000000c
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#define CLOCK_CONTROL_OFF 0x00000000
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enum {
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CMD_READY = 0x01,
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FIFO_READY = 0x02,
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@ -607,19 +613,18 @@ static void jmb38x_ms_reset(struct jmb38x_ms_host *host)
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{
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unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
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writel(host_ctl | HOST_CONTROL_RESET_REQ | HOST_CONTROL_RESET,
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host->addr + HOST_CONTROL);
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writel(HOST_CONTROL_RESET_REQ, host->addr + HOST_CONTROL);
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while (HOST_CONTROL_RESET_REQ
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& (host_ctl = readl(host->addr + HOST_CONTROL))) {
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ndelay(100);
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dev_dbg(&host->chip->pdev->dev, "reset\n");
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ndelay(20);
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dev_dbg(&host->chip->pdev->dev, "reset %08x\n", host_ctl);
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}
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writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
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writel(HOST_CONTROL_RESET, host->addr + HOST_CONTROL);
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mmiowb();
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writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
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dev_dbg(&host->chip->pdev->dev, "reset\n");
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writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
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}
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static void jmb38x_ms_set_param(struct memstick_host *msh,
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@ -627,10 +632,8 @@ static void jmb38x_ms_set_param(struct memstick_host *msh,
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int value)
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{
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struct jmb38x_ms_host *host = memstick_priv(msh);
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unsigned int host_ctl;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
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unsigned int clock_ctl = CLOCK_CONTROL_40MHZ, clock_delay = 0;
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switch (param) {
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case MEMSTICK_POWER:
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@ -638,60 +641,57 @@ static void jmb38x_ms_set_param(struct memstick_host *msh,
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jmb38x_ms_reset(host);
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writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
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: PAD_PU_PD_ON_MS_SOCK0,
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: PAD_PU_PD_ON_MS_SOCK0,
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host->addr + PAD_PU_PD);
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writel(PAD_OUTPUT_ENABLE_MS,
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host->addr + PAD_OUTPUT_ENABLE);
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host_ctl = readl(host->addr + HOST_CONTROL);
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host_ctl |= 7;
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writel(host_ctl | (HOST_CONTROL_POWER_EN
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| HOST_CONTROL_CLOCK_EN),
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host->addr + HOST_CONTROL);
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host_ctl = 7;
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host_ctl |= HOST_CONTROL_POWER_EN
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| HOST_CONTROL_CLOCK_EN;
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writel(host_ctl, host->addr + HOST_CONTROL);
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dev_dbg(&host->chip->pdev->dev, "power on\n");
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} else if (value == MEMSTICK_POWER_OFF) {
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writel(readl(host->addr + HOST_CONTROL)
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& ~(HOST_CONTROL_POWER_EN
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| HOST_CONTROL_CLOCK_EN),
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host->addr + HOST_CONTROL);
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host_ctl &= ~(HOST_CONTROL_POWER_EN
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| HOST_CONTROL_CLOCK_EN);
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writel(host_ctl, host->addr + HOST_CONTROL);
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writel(0, host->addr + PAD_OUTPUT_ENABLE);
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writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
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dev_dbg(&host->chip->pdev->dev, "power off\n");
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}
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break;
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case MEMSTICK_INTERFACE:
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/* jmb38x_ms_reset(host); */
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host_ctl = readl(host->addr + HOST_CONTROL);
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host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
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/* host_ctl |= 7; */
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if (value == MEMSTICK_SERIAL) {
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host_ctl &= ~HOST_CONTROL_FAST_CLK;
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host_ctl |= HOST_CONTROL_IF_SERIAL
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<< HOST_CONTROL_IF_SHIFT;
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host_ctl |= HOST_CONTROL_REI;
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writel(0, host->addr + CLOCK_DELAY);
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clock_ctl = CLOCK_CONTROL_40MHZ;
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clock_delay = 0;
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} else if (value == MEMSTICK_PAR4) {
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host_ctl |= HOST_CONTROL_FAST_CLK;
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host_ctl |= HOST_CONTROL_IF_PAR4
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<< HOST_CONTROL_IF_SHIFT;
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host_ctl &= ~HOST_CONTROL_REI;
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writel(4, host->addr + CLOCK_DELAY);
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clock_ctl = CLOCK_CONTROL_40MHZ;
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clock_delay = 4;
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} else if (value == MEMSTICK_PAR8) {
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host_ctl |= HOST_CONTROL_FAST_CLK;
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host_ctl |= HOST_CONTROL_IF_PAR8
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<< HOST_CONTROL_IF_SHIFT;
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host_ctl &= ~HOST_CONTROL_REI;
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writel(4, host->addr + CLOCK_DELAY);
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clock_ctl = CLOCK_CONTROL_60MHZ;
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clock_delay = 0;
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}
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writel(host_ctl, host->addr + HOST_CONTROL);
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writel(clock_ctl, host->addr + CLOCK_CONTROL);
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writel(clock_delay, host->addr + CLOCK_DELAY);
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break;
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};
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spin_unlock_irqrestore(&host->lock, flags);
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}
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#ifdef CONFIG_PM
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