From aceb6f0b6da20a86516d59f73ecdc7ea3c4a23da Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Sun, 13 May 2007 13:32:23 +0100 Subject: [PATCH 01/22] [ARM] 4375/1: sharpsl_pm: Fix compile warnings Fix compile warnings from sharpsl_pm.c. Attribute registration failure doesn't stop the driver working so just warn about it. Signed-off-by: Richard Purdie Signed-off-by: Russell King --- arch/arm/common/sharpsl_pm.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index 5972df2b9af4..c8e78d96e592 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c @@ -153,7 +153,7 @@ static void sharpsl_battery_thread(struct work_struct *private_) sharpsl_pm.battstat.mainbat_percent = percent; } - dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %d\n", voltage, + dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage, sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies); /* If battery is low. limit backlight intensity to save power. */ @@ -625,7 +625,7 @@ static int sharpsl_fatal_check(void) } temp = get_select_val(buff); - dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %d\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); + dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT)); if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) || (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt))) @@ -774,6 +774,8 @@ static struct pm_ops sharpsl_pm_ops = { static int __init sharpsl_pm_probe(struct platform_device *pdev) { + int ret; + if (!pdev->dev.platform_data) return -EINVAL; @@ -792,8 +794,10 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev) sharpsl_pm.machinfo->init(); - device_create_file(&pdev->dev, &dev_attr_battery_percentage); - device_create_file(&pdev->dev, &dev_attr_battery_voltage); + ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage); + ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage); + if (ret != 0) + dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret); apm_get_power_status = sharpsl_apm_get_power_status; From 8858e9afdf31bab05247b1680b16c65fe7edbbe1 Mon Sep 17 00:00:00 2001 From: Milan Svoboda Date: Mon, 14 May 2007 07:50:42 +0100 Subject: [PATCH 02/22] [ARM] 4376/1: Selects GENERIC_GPIO for ARCH_IXP4XX in Kconfig Selects GENERIC_GPIO for ARCH_IXP4XX in Kconfig. IXP4XX has generic GPIO support; however, ARCH_IXP4XX Kconfig entry currently does not select GENERIC_GPIO like other arch entries. Signed-off-by: Milan Svoboda Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e55bbd32dcac..50d9f3e4e0f1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -287,6 +287,7 @@ config ARCH_IXP2000 config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU + select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS help From e45c7a43825b0feb161ef2ebe5324cd517dd4388 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Mon, 14 May 2007 14:32:43 +0100 Subject: [PATCH 03/22] [ARM] 4378/1: KS8695: Serial driver fix A fix for a really stupid typo in the KS8695 serial driver. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- drivers/serial/serial_ks8695.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c index c5346d677315..698763b28ddd 100644 --- a/drivers/serial/serial_ks8695.c +++ b/drivers/serial/serial_ks8695.c @@ -301,11 +301,11 @@ static int ks8695uart_startup(struct uart_port *port) retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, IRQF_DISABLED, "UART LineStatus", port); if (retval) - return err_ls; + goto err_ls; retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, IRQF_DISABLED, "UART ModemStatus", port); if (retval) - return err_ms; + goto err_ms; return 0; From 06ba255571b0a2f1fb7e49e7406364e4194f4e10 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 14 May 2007 22:56:32 +0100 Subject: [PATCH 04/22] [ARM] Remove Integrator/CP SMP platform support The Integrator/CP SMP platform support was never fully merged, and now it's causing build breakage. Remove it. Signed-off-by: Russell King --- arch/arm/mach-integrator/Makefile | 1 - arch/arm/mach-integrator/core.c | 18 +-- arch/arm/mach-integrator/headsmp.S | 37 ----- arch/arm/mach-integrator/platsmp.c | 204 -------------------------- include/asm-arm/arch-integrator/smp.h | 18 --- 5 files changed, 1 insertion(+), 277 deletions(-) delete mode 100644 arch/arm/mach-integrator/headsmp.S delete mode 100644 arch/arm/mach-integrator/platsmp.c delete mode 100644 include/asm-arm/arch-integrator/smp.h diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index ebb255bdce8a..158daaf9e3b0 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -12,4 +12,3 @@ obj-$(CONFIG_LEDS) += leds.o obj-$(CONFIG_PCI) += pci_v3.o pci.o obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 897c21c2fb5b..e9c82deb791d 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -257,23 +257,7 @@ integrator_timer_interrupt(int irq, void *dev_id) */ writel(1, TIMER1_VA_BASE + TIMER_INTCLR); - /* - * the clock tick routines are only processed on the - * primary CPU - */ - if (hard_smp_processor_id() == 0) { - timer_tick(); -#ifdef CONFIG_SMP - smp_send_timer(); -#endif - } - -#ifdef CONFIG_SMP - /* - * this is the ARM equivalent of the APIC timer interrupt - */ - update_process_times(user_mode(get_irq_regs())); -#endif /* CONFIG_SMP */ + timer_tick(); write_sequnlock(&xtime_lock); diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S deleted file mode 100644 index ceaa88e30d70..000000000000 --- a/arch/arm/mach-integrator/headsmp.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * linux/arch/arm/mach-integrator/headsmp.S - * - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - - __INIT - -/* - * Integrator specific entry point for secondary CPUs. This provides - * a "holding pen" into which all secondary cores are held until we're - * ready for them to initialise. - */ -ENTRY(integrator_secondary_startup) - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - ldr r6, [r6, r4] -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup - -1: .long . - .long phys_pen_release diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c deleted file mode 100644 index 613b841a10f3..000000000000 --- a/arch/arm/mach-integrator/platsmp.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * linux/arch/arm/mach-cintegrator/platsmp.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -extern void integrator_secondary_startup(void); - -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ -volatile int __cpuinitdata pen_release = -1; -unsigned long __cpuinitdata phys_pen_release = 0; - -static DEFINE_SPINLOCK(boot_lock); - -void __cpuinit platform_secondary_init(unsigned int cpu) -{ - /* - * the primary core may have used a "cross call" soft interrupt - * to get this processor out of WFI in the BootMonitor - make - * sure that we are no longer being sent this soft interrupt - */ - smp_cross_call_done(cpumask_of_cpu(cpu)); - - /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - secondary_scan_irqs(); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - pen_release = -1; - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - * - * Note that "pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. - */ - pen_release = cpu; - flush_cache_all(); - - /* - * XXX - * - * This is a later addition to the booting protocol: the - * bootMonitor now puts secondary cores into WFI, so - * poke_milo() no longer gets the cores moving; we need - * to send a soft interrupt to wake the secondary core. - * Use smp_cross_call() for this, since there's little - * point duplicating the code here - */ - smp_cross_call(cpumask_of_cpu(cpu)); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return pen_release != -1 ? -ENOSYS : 0; -} - -static void __init poke_milo(void) -{ - extern void secondary_startup(void); - - /* nobody is to be released from the pen yet */ - pen_release = -1; - - phys_pen_release = virt_to_phys(&pen_release); - - /* - * write the address of secondary startup into the system-wide - * flags register, then clear the bottom two bits, which is what - * BootMonitor is waiting for - */ -#if 1 -#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30 - __raw_writel(virt_to_phys(integrator_secondary_startup), - (IO_ADDRESS(INTEGRATOR_HDR_BASE) + - CINTEGRATOR_HDR_FLAGSS_OFFSET)); -#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34 - __raw_writel(3, - (IO_ADDRESS(INTEGRATOR_HDR_BASE) + - CINTEGRATOR_HDR_FLAGSC_OFFSET)); -#endif - - mb(); -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -void __init smp_init_cpus(void) -{ - unsigned int i, ncores = get_core_count(); - - for (i = 0; i < ncores; i++) - cpu_set(i, cpu_possible_map); -} - -void __init smp_prepare_cpus(unsigned int max_cpus) -{ - unsigned int ncores = get_core_count(); - unsigned int cpu = smp_processor_id(); - int i; - - /* sanity check */ - if (ncores == 0) { - printk(KERN_ERR - "Integrator/CP: strange CM count of 0? Default to 1\n"); - - ncores = 1; - } - - if (ncores > NR_CPUS) { - printk(KERN_WARNING - "Integrator/CP: no. of cores (%d) greater than configured " - "maximum of %d - clipping\n", - ncores, NR_CPUS); - ncores = NR_CPUS; - } - - /* - * start with some more config for the Boot CPU, now that - * the world is a bit more alive (which was not the case - * when smp_prepare_boot_cpu() was called) - */ - smp_store_cpu_info(cpu); - - /* - * are we trying to boot more cores than exist? - */ - if (max_cpus > ncores) - max_cpus = ncores; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - cpu_set(i, cpu_present_map); - - /* - * Do we need any more CPUs? If so, then let them know where - * to start. Note that, on modern versions of MILO, the "poke" - * doesn't actually do anything until each individual core is - * sent a soft interrupt to get it out of WFI - */ - if (max_cpus > 1) - poke_milo(); -} diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h deleted file mode 100644 index ab2c79bb9505..000000000000 --- a/include/asm-arm/arch-integrator/smp.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef ASMARM_ARCH_SMP_H -#define ASMARM_ARCH_SMP_H - - -#include -#include - -#define hard_smp_processor_id() \ - ({ \ - unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5" \ - : "=r" (cpunum)); \ - cpunum &= 0x0F; \ - }) - -extern void secondary_scan_irqs(void); - -#endif From e702a7155d14a6e11645e17d829217ae98fd45bb Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 15 May 2007 01:03:31 +0100 Subject: [PATCH 05/22] [ARM] 4382/1: iop13xx: fix msi support updates iop13xx msi support for a msi api change in 2.6.22 rev7: * update for Michael Ellerman's "MSI: arch must connect the irq and the msi_desc" patch Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/mach-iop13xx/msi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index 2d2369302220..062d2acdd5e5 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -190,5 +190,5 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) write_msi_msg(irq, &msg); set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); - return irq; + return 0; } From d73d8011779292788def2cd2520d6f39d9b406de Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 15 May 2007 01:03:36 +0100 Subject: [PATCH 06/22] [ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files WARNING: arch/arm/mach-iop13xx/built-in.o - Section mismatch: reference to .init.text:iop13xx_pcie_map_irq from .text between 'iop13xx_pci_setup' (at offset 0x7fc) and 'iop13xx_map_pci_memory' While fixing this warning I also recalled Adrian Bunk's recommendation to not use inline in .c files, as 'iop13xx_map_pci_memory' is needlessly inlined. Removing 'inline' uncovered some dead code so that is cleaned up as well. Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/mach-iop13xx/irq.c | 54 ++++++--------------------------- arch/arm/mach-iop13xx/msi.c | 16 +++++----- arch/arm/mach-iop13xx/pci.c | 8 ++--- arch/arm/mach-iop32x/glantank.c | 2 +- arch/arm/mach-iop32x/iq31244.c | 4 +-- arch/arm/mach-iop32x/iq80321.c | 2 +- arch/arm/mach-iop32x/irq.c | 4 +-- arch/arm/mach-iop32x/n2100.c | 2 +- arch/arm/mach-iop33x/iq80331.c | 2 +- arch/arm/mach-iop33x/iq80332.c | 2 +- arch/arm/mach-iop33x/irq.c | 12 ++++---- arch/arm/plat-iop/pci.c | 4 +-- 12 files changed, 38 insertions(+), 74 deletions(-) diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index 5791addd436b..69f07b25b3c9 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -30,77 +30,65 @@ /* INTCTL0 CP6 R0 Page 4 */ -static inline u32 read_intctl_0(void) +static u32 read_intctl_0(void) { u32 val; asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); return val; } -static inline void write_intctl_0(u32 val) +static void write_intctl_0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); } /* INTCTL1 CP6 R1 Page 4 */ -static inline u32 read_intctl_1(void) +static u32 read_intctl_1(void) { u32 val; asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); return val; } -static inline void write_intctl_1(u32 val) +static void write_intctl_1(u32 val) { asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); } /* INTCTL2 CP6 R2 Page 4 */ -static inline u32 read_intctl_2(void) +static u32 read_intctl_2(void) { u32 val; asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); return val; } -static inline void write_intctl_2(u32 val) +static void write_intctl_2(u32 val) { asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); } /* INTCTL3 CP6 R3 Page 4 */ -static inline u32 read_intctl_3(void) +static u32 read_intctl_3(void) { u32 val; asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); return val; } -static inline void write_intctl_3(u32 val) +static void write_intctl_3(u32 val) { asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); } /* INTSTR0 CP6 R0 Page 5 */ -static inline u32 read_intstr_0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val)); - return val; -} -static inline void write_intstr_0(u32 val) +static void write_intstr_0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); } /* INTSTR1 CP6 R1 Page 5 */ -static inline u32 read_intstr_1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val)); - return val; -} static void write_intstr_1(u32 val) { asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); @@ -108,12 +96,6 @@ static void write_intstr_1(u32 val) /* INTSTR2 CP6 R2 Page 5 */ -static inline u32 read_intstr_2(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val)); - return val; -} static void write_intstr_2(u32 val) { asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); @@ -121,12 +103,6 @@ static void write_intstr_2(u32 val) /* INTSTR3 CP6 R3 Page 5 */ -static inline u32 read_intstr_3(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val)); - return val; -} static void write_intstr_3(u32 val) { asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); @@ -134,12 +110,6 @@ static void write_intstr_3(u32 val) /* INTBASE CP6 R0 Page 2 */ -static inline u32 read_intbase(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val)); - return val; -} static void write_intbase(u32 val) { asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); @@ -147,12 +117,6 @@ static void write_intbase(u32 val) /* INTSIZE CP6 R2 Page 2 */ -static inline u32 read_intsize(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val)); - return val; -} static void write_intsize(u32 val) { asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index 062d2acdd5e5..63ef1124ca5c 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); /* IMIPR0 CP6 R8 Page 1 */ -static inline u32 read_imipr_0(void) +static u32 read_imipr_0(void) { u32 val; asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_0(u32 val) +static void write_imipr_0(u32 val) { asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); } /* IMIPR1 CP6 R9 Page 1 */ -static inline u32 read_imipr_1(void) +static u32 read_imipr_1(void) { u32 val; asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_1(u32 val) +static void write_imipr_1(u32 val) { asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); } /* IMIPR2 CP6 R10 Page 1 */ -static inline u32 read_imipr_2(void) +static u32 read_imipr_2(void) { u32 val; asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_2(u32 val) +static void write_imipr_2(u32 val) { asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); } /* IMIPR3 CP6 R11 Page 1 */ -static inline u32 read_imipr_3(void) +static u32 read_imipr_3(void) { u32 val; asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); return val; } -static inline void write_imipr_3(u32 val) +static void write_imipr_3(u32 val) { asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); } diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 1c9e94c38b7e..69e8953832fd 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -144,7 +144,7 @@ void iop13xx_map_pci_memory(void) } } -static inline int iop13xx_atu_function(int atu) +static int iop13xx_atu_function(int atu) { int func = 0; /* the function number depends on the value of the @@ -259,7 +259,7 @@ static int iop13xx_atux_pci_status(int clear) * data. Note that the data dependency on %0 encourages an abort * to be detected before we return. */ -static inline u32 iop13xx_atux_read(unsigned long addr) +static u32 iop13xx_atux_read(unsigned long addr) { u32 val; @@ -387,7 +387,7 @@ static int iop13xx_atue_pci_status(int clear) return err; } -static inline int __init +static int iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) { WARN_ON(idsel != 0); @@ -401,7 +401,7 @@ iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) } } -static inline u32 iop13xx_atue_read(unsigned long addr) +static u32 iop13xx_atue_read(unsigned long addr) { u32 val; diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 45f4f13ae11b..5776fd884115 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -75,7 +75,7 @@ void __init glantank_map_io(void) #define INTC IRQ_IOP32X_XINT2 #define INTD IRQ_IOP32X_XINT3 -static inline int __init +static int __init glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { static int pci_irq_table[][4] = { diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 7b21c6e13e59..d4eefbea1fe6 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -104,7 +104,7 @@ void __init iq31244_map_io(void) /* * EP80219/IQ31244 PCI. */ -static inline int __init +static int __init ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; @@ -140,7 +140,7 @@ static struct hw_pci ep80219_pci __initdata = { .map_irq = ep80219_pci_map_irq, }; -static inline int __init +static int __init iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index bc25fb91e7b9..8d9f49164a84 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -72,7 +72,7 @@ void __init iq80321_map_io(void) /* * IQ80321 PCI. */ -static inline int __init +static int __init iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 82598dc18d80..c971171c2905 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -21,12 +21,12 @@ static u32 iop32x_mask; -static inline void intctl_write(u32 val) +static void intctl_write(u32 val) { asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); } -static inline void intstr_write(u32 val) +static void intstr_write(u32 val) { asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); } diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 5f07344d96f3..d55005d64781 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -76,7 +76,7 @@ void __init n2100_map_io(void) /* * N2100 PCI. */ -static inline int __init +static int __init n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 376c932830be..2b063180687a 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -55,7 +55,7 @@ static struct sys_timer iq80331_timer = { /* * IQ80331 PCI. */ -static inline int __init +static int __init iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 58c81496c6f6..7889ce3cb08e 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -55,7 +55,7 @@ static struct sys_timer iq80332_timer = { /* * IQ80332 PCI. */ -static inline int __init +static int __init iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index c65ea78a2427..f09dd054b9c0 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -22,32 +22,32 @@ static u32 iop33x_mask0; static u32 iop33x_mask1; -static inline void intctl0_write(u32 val) +static void intctl0_write(u32 val) { asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); } -static inline void intctl1_write(u32 val) +static void intctl1_write(u32 val) { asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); } -static inline void intstr0_write(u32 val) +static void intstr0_write(u32 val) { asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); } -static inline void intstr1_write(u32 val) +static void intstr1_write(u32 val) { asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); } -static inline void intbase_write(u32 val) +static void intbase_write(u32 val) { asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); } -static inline void intsize_write(u32 val) +static void intsize_write(u32 val) { asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); } diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index e2744b7227c5..d3605934f1c7 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -88,7 +88,7 @@ static int iop3xx_pci_status(void) * data. Note that the 4 nop's ensure that we are able to handle * a delayed abort (in theory.) */ -static inline u32 iop3xx_read(unsigned long addr) +static u32 iop3xx_read(unsigned long addr) { u32 val; @@ -321,7 +321,7 @@ void __init iop3xx_atu_disable(void) /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ int init_atu; -void iop3xx_pci_preinit(void) +void __init iop3xx_pci_preinit(void) { if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { iop3xx_atu_disable(); From e903382ceae1dd85e650ffc7e98facdd59cc7a3f Mon Sep 17 00:00:00 2001 From: Sandeep Sanjay Patil Date: Wed, 16 May 2007 10:51:45 +0100 Subject: [PATCH 07/22] [ARM] 4384/1: S3C2412/13 SPI registers offset correction Change the SPI Channel 1 register offset in s3c_spi1_resource[], and s3c2412_dma_mappings[]. Offset has to be 0x100 in s3c2412/13's case. Also, total SPI memory resource size changed to 0x24 for s3c2412/13. Signed-off-by: Sandeep Patil Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2412/dma.c | 4 ++-- arch/arm/mach-s3c2412/s3c2412.c | 9 +++++++++ arch/arm/plat-s3c24xx/devs.c | 5 +++-- include/asm-arm/arch-s3c2410/regs-spi.h | 2 ++ 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index d0f4695c09d9..668cccefe7b0 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -59,8 +59,8 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { [DMACH_SPI1] = { .name = "spi1", .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), - .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, + .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT, }, [DMACH_UART0] = { .name = "uart0", diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index aafe0bc593f1..c602aa39f9c4 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -74,6 +75,14 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) s3c_device_sdi.name = "s3c2412-sdi"; s3c_device_lcd.name = "s3c2412-lcd"; s3c_device_nand.name = "s3c2412-nand"; + + /* spi channel related changes, s3c2412/13 specific */ + s3c_device_spi0.name = "s3c2412-spi"; + s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24; + s3c_device_spi1.name = "s3c2412-spi"; + s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1; + s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24; + } /* s3c2412_idle diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 0fe53b39cb2f..8eca9599ef60 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -33,6 +33,7 @@ #include #include +#include /* Serial port registrations */ @@ -437,8 +438,8 @@ EXPORT_SYMBOL(s3c_device_spi0); static struct resource s3c_spi1_resource[] = { [0] = { - .start = S3C24XX_PA_SPI + 0x20, - .end = S3C24XX_PA_SPI + 0x20 + 0x1f, + .start = S3C24XX_PA_SPI + S3C2410_SPI1, + .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h index 3552280d1e8f..4a499a138256 100644 --- a/include/asm-arm/arch-s3c2410/regs-spi.h +++ b/include/asm-arm/arch-s3c2410/regs-spi.h @@ -12,6 +12,8 @@ #ifndef __ASM_ARCH_REGS_SPI_H #define __ASM_ARCH_REGS_SPI_H +#define S3C2410_SPI1 (0x20) +#define S3C2412_SPI1 (0x100) #define S3C2410_SPCON (0x00) From c05107911a38235fec87892d83dc54aba9aaf3bd Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 16 May 2007 12:41:15 +0100 Subject: [PATCH 08/22] [ARM] Update ARM syscalls Add utimensat, signalfd, timerfd, eventfd syscalls. Add ignore defines for sync_file_range and fadvise64_64 which we implement differently. Signed-off-by: Russell King --- arch/arm/kernel/calls.S | 4 ++++ include/asm-arm/unistd.h | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index ae89cdd82b16..19326d7cdeb3 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -357,6 +357,10 @@ /* 345 */ CALL(sys_getcpu) CALL(sys_ni_syscall) /* eventually epoll_pwait */ CALL(sys_kexec_load) + CALL(sys_utimensat) + CALL(sys_signalfd) +/* 350 */ CALL(sys_timerfd) + CALL(sys_eventfd) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index c025ab47e4b9..250d7f145aca 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h @@ -373,6 +373,10 @@ #define __NR_getcpu (__NR_SYSCALL_BASE+345) /* 346 for epoll_pwait */ #define __NR_kexec_load (__NR_SYSCALL_BASE+347) +#define __NR_utimensat (__NR_SYSCALL_BASE+348) +#define __NR_signalfd (__NR_SYSCALL_BASE+349) +#define __NR_timerfd (__NR_SYSCALL_BASE+350) +#define __NR_eventfd (__NR_SYSCALL_BASE+351) /* * The following SWIs are ARM private. @@ -433,5 +437,11 @@ */ #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") +/* + * Unimplemented (or alternatively implemented) syscalls + */ +#define __IGNORE_sync_file_range 1 +#define __IGNORE_fadvise64_64 1 + #endif /* __KERNEL__ */ #endif /* __ASM_ARM_UNISTD_H */ From f3270f6ef7d60251617f9d4c08f76ec01c647aa4 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 16 May 2007 17:36:17 +0100 Subject: [PATCH 09/22] [ARM] Silence OMAP kernel configuration warning arch/arm/mach-omap1/Kconfig:41:warning: 'select' used by config symbol 'MACH_OMAP_H3' refers to undefined symbol 'GPIOEXPANDER_OMAP' Signed-off-by: Russell King --- arch/arm/mach-omap1/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 856c681ebbbc..f6ecdd3a2478 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -38,7 +38,7 @@ config MACH_OMAP_H2 config MACH_OMAP_H3 bool "TI H3 Support" depends on ARCH_OMAP1 && ARCH_OMAP16XX - select GPIOEXPANDER_OMAP +# select GPIOEXPANDER_OMAP help TI OMAP 1710 H3 board support. Say Y here if you have such a board. From 0f347bb9136f55ff575d55441a29e92c16e87fb0 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 17 May 2007 10:11:34 +0100 Subject: [PATCH 10/22] [ARM] gic: Fix gic cascade irq handling No need for the cascade irq function to have a "fastcall" annotation. Fix the range checking for valid IRQ numbers - comparing the value returned by the GIC with NR_IRQS is meaningless since we translate the GIC irq number to a Linux IRQ number afterwards. Check the GIC returned IRQ number is within limits first, then add the IRQ offset, and only then compare with NR_IRQS. Signed-off-by: Russell King --- arch/arm/common/gic.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4deece5fbdf4..2ae0bd1c907d 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val) } #endif -static void fastcall gic_handle_cascade_irq(unsigned int irq, - struct irq_desc *desc) +static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { struct gic_chip_data *chip_data = get_irq_data(irq); struct irq_chip *chip = get_irq_chip(irq); - unsigned int cascade_irq; + unsigned int cascade_irq, gic_irq; unsigned long status; /* primary controller ack'ing */ @@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq, status = readl(chip_data->cpu_base + GIC_CPU_INTACK); spin_unlock(&irq_controller_lock); - cascade_irq = (status & 0x3ff); - if (cascade_irq > 1020) + gic_irq = (status & 0x3ff); + if (gic_irq == 1023) goto out; - if (cascade_irq < 32 || cascade_irq >= NR_IRQS) { - do_bad_IRQ(cascade_irq, desc); - goto out; - } - cascade_irq += chip_data->irq_offset; - generic_handle_irq(cascade_irq); + cascade_irq = gic_irq + chip_data->irq_offset; + if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) + do_bad_IRQ(cascade_irq, desc); + else + generic_handle_irq(cascade_irq); out: /* primary controller unmasking */ From c6af66b9fe93990c70aaee53ce3ce7e53a83676a Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 17 May 2007 10:16:55 +0100 Subject: [PATCH 11/22] [ARM] integrator: fix pci_v3 compile error with DEBUG_LL If DEBUG_LL is enabled, we want to use get_irq_regs(), but this causes a build error due to the inline function missing. Add the necessary header file. Signed-off-by: Russell King --- arch/arm/mach-integrator/pci_v3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index af9ebccac7c1..d4d8134ce567 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -33,6 +33,7 @@ #include #include #include +#include #include From 516793c61b3db1f60e0b0d0e3c382bcca9ae84fd Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 17 May 2007 10:19:23 +0100 Subject: [PATCH 12/22] [ARM] ARMv6: add CPU_HAS_ASID configuration Presently, we check for the minimum ARM architecture that we're building for to determine whether we need ASID support. This is wrong - if we're going to support a range of CPUs which include ARMv6 or higher, we need the ASID. Convert the checks to use a new configuration symbol, and arrange for ARMv6 and higher CPU entries to select it. Signed-off-by: Russell King --- arch/arm/kernel/asm-offsets.c | 2 +- arch/arm/mm/Kconfig | 8 ++++++++ include/asm-arm/mmu.h | 4 ++-- include/asm-arm/mmu_context.h | 2 +- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 3c078e346753..3278e713c32a 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -85,7 +85,7 @@ int main(void) DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); BLANK(); -#if __LINUX_ARM_ARCH__ >= 6 +#ifdef CONFIG_CPU_HAS_ASID DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); BLANK(); #endif diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 15f0284010ca..5f472a8b406a 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -351,6 +351,7 @@ config CPU_V6 select CPU_CACHE_V6 select CPU_CACHE_VIPT select CPU_CP15_MMU + select CPU_HAS_ASID select CPU_COPY_V6 if MMU select CPU_TLB_V6 if MMU @@ -376,6 +377,7 @@ config CPU_V7 select CPU_CACHE_V7 select CPU_CACHE_VIPT select CPU_CP15_MMU + select CPU_HAS_ASID select CPU_COPY_V6 if MMU select CPU_TLB_V6 if MMU @@ -498,6 +500,12 @@ config CPU_TLB_V6 endif +config CPU_HAS_ASID + bool + help + This indicates whether the CPU has the ASID register; used to + tag TLB and possibly cache entries. + config CPU_CP15 bool help diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h index fe2a23b5627b..53099d4ee421 100644 --- a/include/asm-arm/mmu.h +++ b/include/asm-arm/mmu.h @@ -4,13 +4,13 @@ #ifdef CONFIG_MMU typedef struct { -#if __LINUX_ARM_ARCH__ >= 6 +#ifdef CONFIG_CPU_HAS_ASID unsigned int id; #endif unsigned int kvm_seq; } mm_context_t; -#if __LINUX_ARM_ARCH__ >= 6 +#ifdef CONFIG_CPU_HAS_ASID #define ASID(mm) ((mm)->context.id & 255) #else #define ASID(mm) (0) diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h index 4981ad419198..6913d02ca5d6 100644 --- a/include/asm-arm/mmu_context.h +++ b/include/asm-arm/mmu_context.h @@ -20,7 +20,7 @@ void __check_kvm_seq(struct mm_struct *mm); -#if __LINUX_ARM_ARCH__ >= 6 +#ifdef CONFIG_CPU_HAS_ASID /* * On ARMv6, we have the following structure in the Context ID: From 1d28bff7c4ea138032b44d514351b7caceb9fba5 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 17 May 2007 06:12:22 +0100 Subject: [PATCH 13/22] [ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts Fix the formating of the "CPU part" field to be consistent with the other fields for pre-ARM7 parts. One tab to many for them to all line up. Signed-off-by: Greg Ungerer Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 0453dcc757b4..650eac1bc0a6 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -918,7 +918,7 @@ static int c_show(struct seq_file *m, void *v) if ((processor_id & 0x0008f000) == 0x00000000) { /* pre-ARM7 */ - seq_printf(m, "CPU part\t\t: %07x\n", processor_id >> 4); + seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4); } else { if ((processor_id & 0x0008f000) == 0x00007000) { /* ARM7 */ From 95ba71f76f1cce550cb2e2b345a204d4a926d29c Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 17 May 2007 06:22:41 +0100 Subject: [PATCH 14/22] [ARM] 4388/1: no need for arm/mm mmap range checks for non-mmu We don't need valid_phys_addr_range() or valid_mmap_phys_addr_range() for the !CONFIG_MMU case. Signed-off-by: Greg Ungerer Signed-off-by: Russell King --- include/asm-arm/io.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 8261ff9e7955..1d3caa42a386 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -259,9 +259,11 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); #define BIOVEC_MERGEABLE(vec1, vec2) \ ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) +#ifdef CONFIG_MMU #define ARCH_HAS_VALID_PHYS_ADDR_RANGE extern int valid_phys_addr_range(unsigned long addr, size_t size); extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); +#endif /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem From 333a42e1f4c5c5c2ed7c652254c35b9e98d5c789 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 20 May 2007 11:55:53 +0100 Subject: [PATCH 15/22] [ARM] 4395/1: S3C24XX: add include of to relevant machines Include in any machines that use the PM functions which require struct sys_device. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/mach-h1940.c | 1 + arch/arm/mach-s3c2410/mach-qt2410.c | 1 + arch/arm/mach-s3c2440/mach-rx3715.c | 1 + arch/arm/plat-s3c24xx/common-smdk.c | 1 + arch/arm/plat-s3c24xx/pm-simtec.c | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 5ccd0be23a33..5c9bcea74767 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 9cc4253d7bbc..d86e6f18bac9 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index c3cc4bf158f6..866ff71c01dd 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 908efa7d745f..1dd60a689ae5 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c index bd965f2feeca..cb0b3a4ccf1b 100644 --- a/arch/arm/plat-s3c24xx/pm-simtec.c +++ b/arch/arm/plat-s3c24xx/pm-simtec.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include From 67364334681503655fbff6c2f2dacfb17f04cadc Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 20 May 2007 17:17:32 +0100 Subject: [PATCH 16/22] [ARM] 4396/1: S3C2443: Add missing HCLK clocks Add the clocks missing form HCLKCON back into the set of clocks being registered at initalisation time. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2443/clock.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 0b6e360aeae7..5955efb5de8d 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -746,6 +746,25 @@ static struct clk init_clocks[] = { .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_USBD, + }, { + .name = "hsmmc", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_HSMMC, + }, { + .name = "cfc", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_CFC, + .ctrlbit = S3C2443_HCLKCON_HSMMC, + }, { + .name = "ssmc", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_SSMC, }, { .name = "timers", .id = -1, @@ -791,7 +810,8 @@ static struct clk init_clocks[] = { .name = "usb-bus-host", .id = -1, .parent = &clk_usb_bus_host, - }, { .name = "ac97", + }, { + .name = "ac97", .id = -1, .parent = &clk_p, .ctrlbit = S3C2443_PCLKCON_AC97, From 5f2ef21703564d3e6f18fd92f2e72f723a5c3402 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 20 May 2007 17:32:39 +0100 Subject: [PATCH 17/22] [ARM] 4397/1: S3C2443: remove SDI0/1 IRQ ambiguity Change the name of the S3C2443_SDI1 to S3C2443_HSMMC to ensure that it is correctly identified. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/irqs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h index c79cb1819913..3b49cd1c345c 100644 --- a/include/asm-arm/arch-s3c2410/irqs.h +++ b/include/asm-arm/arch-s3c2410/irqs.h @@ -124,7 +124,7 @@ #define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ #define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ #define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ -#define IRQ_S3C2443_SDI1 S3C2410_IRQ(20) /* IRQ_SDI */ +#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) From 7e966f3c392ffb5297a6ba0ea701d6a20d1d7292 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 20 May 2007 18:02:50 +0100 Subject: [PATCH 18/22] [ARM] 4398/1: S3C2443: Fix watchdog IRQ number Fix the IRQ number for watchdog on S3C2443 Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2443/s3c2443.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index 11b1d0b310c3..8d8117158d23 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -63,6 +63,10 @@ int __init s3c2443_init(void) s3c_device_nand.name = "s3c2412-nand"; + /* change WDT IRQ number */ + s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT; + s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT; + return sysdev_register(&s3c2443_sysdev); } From 42482e3c77bcb310affdf13e92b93f077d44a7fc Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 20 May 2007 19:58:10 +0100 Subject: [PATCH 19/22] [ARM] 4399/2: S3C2443: Fix SMDK2443 nand timings Reduce the Twrph0 timing slightly to fit on an SMDK2443. This should still produce valid timings for the NAND devices as it is still over the smallest device fitted to these boards. Signed-off-by: Ben Dooks <(address hidden)> Signed-off-by: Russell King --- arch/arm/plat-s3c24xx/common-smdk.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 1dd60a689ae5..7ed19b23ce56 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include @@ -193,6 +194,9 @@ void __init smdk_machine_init(void) s3c2410_gpio_setpin(S3C2410_GPF6, 1); s3c2410_gpio_setpin(S3C2410_GPF7, 1); + if (machine_is_smdk2443()) + smdk_nand_info.twrph0 = 50; + s3c_device_nand.dev.platform_data = &smdk_nand_info; platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); From 69e9c93d0d7d9dfa6bdf5144274dbe65a627b63a Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 20 May 2007 18:13:32 +0100 Subject: [PATCH 20/22] [ARM] 4400/1: S3C24XX: Add high-speed MMC device definition Add definition for high-speed MMC/SD device and add to SMDK2443 device list. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2443/mach-smdk2443.c | 1 + arch/arm/plat-s3c24xx/devs.c | 30 +++++++++++++++++++++++++++ include/asm-arm/plat-s3c24xx/devs.h | 1 + 3 files changed, 32 insertions(+) diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index b71ee53c2865..b1eb709ee65a 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c @@ -104,6 +104,7 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = { static struct platform_device *smdk2443_devices[] __initdata = { &s3c_device_wdt, &s3c_device_i2c, + &s3c_device_hsmmc, }; static void __init smdk2443_map_io(void) diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 8eca9599ef60..5875da0ae0eb 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -403,6 +403,36 @@ struct platform_device s3c_device_sdi = { EXPORT_SYMBOL(s3c_device_sdi); +/* High-speed MMC/SD */ + +static struct resource s3c_hsmmc_resource[] = { + [0] = { + .start = S3C2443_PA_HSMMC, + .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3C2443_HSMMC, + .end = IRQ_S3C2443_HSMMC, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_hsmmc = { + .name = "s3c-sdhci", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), + .resource = s3c_hsmmc_resource, + .dev = { + .dma_mask = &s3c_device_hsmmc_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + + + /* SPI (0) */ static struct resource s3c_spi0_resource[] = { diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h index dddf485fc067..f9d6f0317bc1 100644 --- a/include/asm-arm/plat-s3c24xx/devs.h +++ b/include/asm-arm/plat-s3c24xx/devs.h @@ -29,6 +29,7 @@ extern struct platform_device s3c_device_iis; extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; +extern struct platform_device s3c_device_hsmmc; extern struct platform_device s3c_device_spi0; extern struct platform_device s3c_device_spi1; From fc432e1952a3899ce35e84b417e5d60f74cb901b Mon Sep 17 00:00:00 2001 From: Mariusz Kozlowski Date: Sat, 19 May 2007 00:39:36 +0200 Subject: [PATCH 21/22] [ARM] at91_adc parenthesis balance Trivial unbalanced parenthesis macro fix. Signed-off-by: Mariusz Kozlowski Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91_adc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-arm/arch-at91/at91_adc.h b/include/asm-arm/arch-at91/at91_adc.h index 1ed66eaaf83a..6d71ea2637b1 100644 --- a/include/asm-arm/arch-at91/at91_adc.h +++ b/include/asm-arm/arch-at91/at91_adc.h @@ -55,7 +55,7 @@ #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ -#define AT91_ADC_CHR(n) (0x30 + ((n) * 4) /* Channel Data Register N */ +#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ #define AT91_ADC_DATA (0x3ff) #endif From 6cbdc8c5357276307a77deeada3f04626ff17da6 Mon Sep 17 00:00:00 2001 From: Simon Arlott Date: Fri, 11 May 2007 20:40:30 +0100 Subject: [PATCH 22/22] [ARM] spelling fixes Spelling fixes in arch/arm/. Signed-off-by: Simon Arlott Signed-off-by: Russell King --- arch/arm/common/dmabounce.c | 2 +- arch/arm/common/gic.c | 2 +- arch/arm/common/sharpsl_param.c | 2 +- arch/arm/common/sharpsl_pm.c | 10 +++++----- arch/arm/kernel/sys_arm.c | 2 +- arch/arm/lib/bitops.h | 2 +- arch/arm/mach-at91/board-carmeva.c | 8 ++++---- arch/arm/mach-h720x/cpu-h7202.c | 4 ++-- arch/arm/mach-imx/cpufreq.c | 2 +- arch/arm/mach-imx/dma.c | 8 ++++---- arch/arm/mach-iop13xx/pci.c | 2 +- arch/arm/mach-ixp2000/enp2611.c | 2 +- arch/arm/mach-ixp2000/ixdp2x00.c | 4 ++-- arch/arm/mach-ixp2000/ixdp2x01.c | 6 +++--- arch/arm/mach-ixp2000/pci.c | 2 +- arch/arm/mach-ixp23xx/core.c | 2 +- arch/arm/mach-ixp4xx/gtwx5715-setup.c | 2 +- arch/arm/mach-lh7a40x/lcd-panel.h | 6 +++--- arch/arm/mach-ns9xxx/time.c | 2 +- arch/arm/mach-omap1/board-osk.c | 2 +- arch/arm/mach-omap1/board-palmte.c | 2 +- arch/arm/mach-omap1/pm.c | 2 +- arch/arm/mach-omap2/clock.c | 2 +- arch/arm/mach-omap2/clock.h | 4 ++-- arch/arm/mach-pxa/corgi_lcd.c | 10 +++++----- arch/arm/mach-pxa/corgi_ssp.c | 2 +- arch/arm/mach-realview/localtimer.c | 2 +- arch/arm/mach-s3c2440/mach-osiris.c | 2 +- arch/arm/mach-sa1100/time.c | 2 +- arch/arm/mm/alignment.c | 2 +- arch/arm/mm/ioremap.c | 2 +- arch/arm/mm/mmu.c | 2 +- arch/arm/plat-iop/pci.c | 2 +- arch/arm/plat-omap/common.c | 2 +- arch/arm/plat-omap/dma.c | 2 +- arch/arm/plat-omap/sram.c | 6 +++--- arch/arm/plat-omap/usb.c | 2 +- arch/arm/plat-s3c24xx/dma.c | 2 +- arch/arm/plat-s3c24xx/pm.c | 2 +- 39 files changed, 62 insertions(+), 62 deletions(-) diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 6fbe7722aa44..b36b1e8a105d 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -6,7 +6,7 @@ * copy data to/from buffers located outside the DMA region. This * only works for systems in which DMA memory is at the bottom of * RAM, the remainder of memory is at the top and the DMA memory - * can be marked as ZONE_DMA. Anything beyond that such as discontigous + * can be marked as ZONE_DMA. Anything beyond that such as discontiguous * DMA windows will require custom implementations that reserve memory * areas at early bootup. * diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 2ae0bd1c907d..0c89bd35e06f 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq) * unmask it, in the same way we need to unmask an interrupt when * we first enable it. * - * The GIC has a seperate notion of "end of interrupt" to re-enable + * The GIC has a separate notion of "end of interrupt" to re-enable * an interrupt after handling, in order to support hardware * prioritisation. * diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c index c94864c5b1af..aad4d94ba8f5 100644 --- a/arch/arm/common/sharpsl_param.c +++ b/arch/arm/common/sharpsl_param.c @@ -20,7 +20,7 @@ * typically including LCD parameters are loaded by the bootloader at the * address PARAM_BASE. As the kernel will overwrite them, we need to store * them early in the boot process, then pass them to the appropriate drivers. - * Not all devices use all paramaters but the format is common to all. + * Not all devices use all parameters but the format is common to all. */ #ifdef CONFIG_ARCH_SA1100 #define PARAM_BASE 0xe8ffc000 diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index c8e78d96e592..3bf3a927ae22 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c @@ -291,7 +291,7 @@ static void sharpsl_chrg_full_timer(unsigned long data) } /* Charging Finished Interrupt (Not present on Corgi) */ -/* Can trigger at the same time as an AC staus change so +/* Can trigger at the same time as an AC status change so delay until after that has been processed */ irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id) { @@ -635,7 +635,7 @@ static int sharpsl_fatal_check(void) static int sharpsl_off_charge_error(void) { - dev_err(sharpsl_pm.dev, "Offline Charger: Error occured.\n"); + dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n"); sharpsl_pm.machinfo->charge(0); sharpsl_pm_led(SHARPSL_LED_ERROR); sharpsl_pm.charge_mode = CHRG_ERROR; @@ -691,14 +691,14 @@ static int sharpsl_off_charge_battery(void) time = RCNR; while(1) { - /* Check if any wakeup event had occured */ + /* Check if any wakeup event had occurred */ if (sharpsl_pm.machinfo->charger_wakeup() != 0) return 0; /* Check for timeout */ if ((RCNR - time) > SHARPSL_WAIT_CO_TIME) return 1; if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) { - dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occured. Retrying to check\n"); + dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n"); sharpsl_pm.full_count++; sharpsl_pm.machinfo->charge(0); mdelay(SHARPSL_CHARGE_WAIT_TIME); @@ -714,7 +714,7 @@ static int sharpsl_off_charge_battery(void) time = RCNR; while(1) { - /* Check if any wakeup event had occured */ + /* Check if any wakeup event had occurred */ if (sharpsl_pm.machinfo->charger_wakeup() != 0) return 0; /* Check for timeout */ diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index 3d4fcbc16276..1ca2d5174fcb 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -320,7 +320,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[]) EXPORT_SYMBOL(kernel_execve); /* - * Since loff_t is a 64 bit type we avoid a lot of ABI hastle + * Since loff_t is a 64 bit type we avoid a lot of ABI hassle * with a different argument ordering. */ asmlinkage long sys_arm_fadvise64_64(int fd, int advice, diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h index 542251021744..2e787d40d599 100644 --- a/arch/arm/lib/bitops.h +++ b/arch/arm/lib/bitops.h @@ -47,7 +47,7 @@ * @store: store instruction * * Note: we can trivially conditionalise the store instruction - * to avoid dirting the data cache. + * to avoid dirtying the data cache. */ .macro testop, instr, store add r1, r1, r0, lsr #3 diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index b4518619063a..76ec856cd4f9 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -79,7 +79,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = { .pullup_pin = AT91_PIN_PD9, }; -/* FIXME: user dependend */ +/* FIXME: user dependant */ // static struct at91_cf_data __initdata carmeva_cf_data = { // .det_pin = AT91_PIN_PB0, // .rst_pin = AT91_PIN_PC5, @@ -100,17 +100,17 @@ static struct spi_board_info carmeva_spi_devices[] = { .chip_select = 0, .max_speed_hz = 10 * 1000 * 1000, }, - { /* User accessable spi - cs1 (250KHz) */ + { /* User accessible spi - cs1 (250KHz) */ .modalias = "spi-cs1", .chip_select = 1, .max_speed_hz = 250 * 1000, }, - { /* User accessable spi - cs2 (1MHz) */ + { /* User accessible spi - cs2 (1MHz) */ .modalias = "spi-cs2", .chip_select = 2, .max_speed_hz = 1 * 1000 * 1000, }, - { /* User accessable spi - cs3 (10MHz) */ + { /* User accessible spi - cs3 (10MHz) */ .modalias = "spi-cs3", .chip_select = 3, .max_speed_hz = 10 * 1000 * 1000, diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index 82e420d6fd19..0a1a25fb8ba8 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -143,7 +143,7 @@ h7202_timer_interrupt(int irq, void *dev_id) } /* - * mask multiplexed timer irq's + * mask multiplexed timer IRQs */ static void inline mask_timerx_irq (u32 irq) { @@ -153,7 +153,7 @@ static void inline mask_timerx_irq (u32 irq) } /* - * unmask multiplexed timer irq's + * unmask multiplexed timer IRQs */ static void inline unmask_timerx_irq (u32 irq) { diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c index 7e70e0b0b989..467d899fbe75 100644 --- a/arch/arm/mach-imx/cpufreq.c +++ b/arch/arm/mach-imx/cpufreq.c @@ -245,7 +245,7 @@ static int imx_set_target(struct cpufreq_policy *policy, if(mpctl0) { CSCR |= CSCR_MPLL_RESTART; - /* Wait until MPLL is stablized */ + /* Wait until MPLL is stabilized */ while( CSCR & CSCR_MPLL_RESTART ); imx_set_async_mode(); diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c index 6d50d85a618c..bc6fb02d213b 100644 --- a/arch/arm/mach-imx/dma.c +++ b/arch/arm/mach-imx/dma.c @@ -131,7 +131,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch, * The function setups DMA channel source and destination addresses for transfer * specified by provided parameters. The scatter-gather emulation is disabled, * because linear data block - * form the physical address range is transfered. + * form the physical address range is transferred. * Return value: if incorrect parameters are provided -%EINVAL. * Zero indicates success. */ @@ -192,7 +192,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory * or %DMA_MODE_WRITE from memory to the device * - * The function setups DMA channel state and registers to be ready for transfer + * The function sets up DMA channel state and registers to be ready for transfer * specified by provided parameters. The scatter-gather emulation is set up * according to the parameters. * @@ -212,7 +212,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, * * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x * - * Be carefull there and do not mistakenly mix source and target device + * Be careful here and do not mistakenly mix source and target device * port sizes constants, they are really different: * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 @@ -495,7 +495,7 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) /* * The cleaning of @sg field would be questionable * there, because its value can help to compute - * remaining/transfered bytes count in the handler + * remaining/transferred bytes count in the handler */ /*imx_dma_channels[i].sg = NULL;*/ diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 69e8953832fd..306f82ee57f0 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -989,7 +989,7 @@ void __init iop13xx_pci_init(void) "imprecise external abort"); } -/* intialize the pci memory space. handle any combination of +/* initialize the pci memory space. handle any combination of * atue and atux enabled/disabled */ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c index 500e997ba7a4..9c49435d42c3 100644 --- a/arch/arm/mach-ixp2000/enp2611.c +++ b/arch/arm/mach-ixp2000/enp2611.c @@ -198,7 +198,7 @@ subsys_initcall(enp2611_pci_init); /************************************************************************* - * ENP-2611 Machine Intialization + * ENP-2611 Machine Initialization *************************************************************************/ static struct flash_platform_data enp2611_flash_platform_data = { .map_name = "cfi_probe", diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 52b368b34346..011065b967b4 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -195,7 +195,7 @@ void __init ixdp2x00_map_io(void) * instances of the kernel. So far so good. Peers on the PCI bus running * Linux is a common design in telecom systems. The problem is that instead * of all the devices being controlled by a single host, different - * devices are controlles by different NPUs on the same bus, leading to + * devices are controlled by different NPUs on the same bus, leading to * multiple hosts on the bus. The exact bus layout looks like: * * Bus 0 @@ -211,7 +211,7 @@ void __init ixdp2x00_map_io(void) * | | | | | * ... Dev PMC Media Eth0 Eth1 ... * - * The master controlls all but Eth1, which is controlled by the + * The master controls all but Eth1, which is controlled by the * slave. What this means is that the both the master and the slave * have to scan the bus, but only one of them can enumerate the bus. * In addition, after the bus is scanned, each kernel must remove diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 3084a5fa751c..d3d730d2fc2b 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -276,7 +276,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* Device is located after first MB bridge */ case 0x0008: if (tmp_bus == dev->bus) { - /* Device is located directy after first MB bridge */ + /* Device is located directly after first MB bridge */ switch (devpin) { case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ if (machine_is_ixdp2401()) @@ -299,7 +299,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) break; case 0x0010: if (tmp_bus == dev->bus) { - /* Device is located directy after second MB bridge */ + /* Device is located directly after second MB bridge */ /* Secondary bus of second bridge */ switch (devpin) { case DEVPIN(0, 1): /* DB#0 */ @@ -348,7 +348,7 @@ int __init ixdp2x01_pci_init(void) subsys_initcall(ixdp2x01_pci_init); /************************************************************************* - * IXDP2x01 Machine Intialization + * IXDP2x01 Machine Initialization *************************************************************************/ static struct flash_platform_data ixdp2x01_flash_platform_data = { .map_name = "cfi_probe", diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c index 5a09a90c08fb..03f4cf7f9dec 100644 --- a/arch/arm/mach-ixp2000/pci.c +++ b/arch/arm/mach-ixp2000/pci.c @@ -102,7 +102,7 @@ int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, } /* - * We don't do error checks by callling clear_master_aborts() b/c the + * We don't do error checks by calling clear_master_aborts() b/c the * assumption is that the caller did a read first to make sure a device * exists. */ diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index b644bbab7d0a..16356ffc86ae 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c @@ -389,7 +389,7 @@ struct sys_timer ixp23xx_timer = { /************************************************************************* - * IXP23xx Platform Initializaion + * IXP23xx Platform Initialization *************************************************************************/ static struct resource ixp23xx_uart_resources[] = { { diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 30f1300e0e21..dc6725bda3c4 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-ixp4xx/gtwx5715-setup.c * - * Gemtek GTWX5715 (Linksys WRV54G) board settup + * Gemtek GTWX5715 (Linksys WRV54G) board setup * * Copyright (C) 2004 George T. Joseph * Derived from Coyote diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h index 4fb2efc4950f..df6e38ed425b 100644 --- a/arch/arm/mach-lh7a40x/lcd-panel.h +++ b/arch/arm/mach-lh7a40x/lcd-panel.h @@ -126,7 +126,7 @@ static struct clcd_panel_extra lcd_panel_extra = { */ -/* The full horozontal cycle (Th) is clock/360/400/450. */ +/* The full horizontal cycle (Th) is clock/360/400/450. */ /* The full vertical cycle (Tv) is line/251/262/280. */ #define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */ @@ -162,7 +162,7 @@ static struct clcd_panel lcd_panel = { /* Logic Product Development LCD 6.4" VGA -10 */ /* Sharp PN LQ64D343 */ -/* The full horozontal cycle (Th) is clock/750/800/900. */ +/* The full horizontal cycle (Th) is clock/750/800/900. */ /* The full vertical cycle (Tv) is line/515/525/560. */ #define PIX_CLOCK_TARGET (28330000) @@ -243,7 +243,7 @@ static struct clcd_panel lcd_panel = { * (fdisk, e2fsck). And, at that speed the display may have a visible * flicker. */ -/* The full horozontal cycle (Th) is clock/832/1056/1395. */ +/* The full horizontal cycle (Th) is clock/832/1056/1395. */ #define PIX_CLOCK_TARGET (20000000) #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c index dd257084441c..b97d0c54a388 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time.c @@ -35,7 +35,7 @@ static unsigned long ns9xxx_timer_gettimeoffset(void) { /* return the microseconds which have passed since the last interrupt * was _serviced_. That is, if an interrupt is pending or the counter - * reloads, return one periode more. */ + * reloads, return one period more. */ u32 counter1 = SYS_TR(0); int pending = SYS_ISR & (1 << IRQ_TIMER0); diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7d0cf7af88ce..e7130293a03f 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -385,7 +385,7 @@ static void __init osk_init(void) /* Workaround for wrong CS3 (NOR flash) timing * There are some U-Boot versions out there which configure * wrong CS3 memory timings. This mainly leads to CRC - * or similiar errors if you use NOR flash (e.g. with JFFS2) + * or similar errors if you use NOR flash (e.g. with JFFS2) */ if (EMIFS_CCS(3) != EMIFS_CS3_VAL) EMIFS_CCS(3) = EMIFS_CS3_VAL; diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 4bc8a62909b9..015824185629 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -7,7 +7,7 @@ * * Original version : Laurent Gonzalez * - * Maintainters : http://palmtelinux.sf.net + * Maintainers : http://palmtelinux.sf.net * palmtelinux-developpers@lists.sf.net * * This program is free software; you can redistribute it and/or modify diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 8caee68aa090..5bb348e2e315 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -438,7 +438,7 @@ void omap_pm_suspend(void) omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); /* - * Reenable interrupts + * Re-enable interrupts */ local_irq_enable(); diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 5170481afeab..588adb5ab47f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -443,7 +443,7 @@ static long omap2_clk_round_rate(struct clk *clk, unsigned long rate) /* * Check the DLL lock state, and return tue if running in unlock mode. - * This is needed to compenste for the shifted DLL value in unlock mode. + * This is needed to compensate for the shifted DLL value in unlock mode. */ static u32 omap2_dll_force_needed(void) { diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 162978fd5359..4f791866b910 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -338,7 +338,7 @@ struct prcm_config { /* * These represent optimal values for common parts, it won't work for all. * As long as you scale down, most parameters are still work, they just - * become sub-optimal. The RFR value goes in the oppisite direction. If you + * become sub-optimal. The RFR value goes in the opposite direction. If you * don't adjust it down as your clock period increases the refresh interval * will not be met. Setting all parameters for complete worst case may work, * but may cut memory performance by 2x. Due to errata the DLLs need to be @@ -384,7 +384,7 @@ struct prcm_config { * Filling in table based on H4 boards and 2430-SDPs variants available. * There are quite a few more rates combinations which could be defined. * - * When multiple values are defiend the start up will try and choose the + * When multiple values are defined the start up will try and choose the * fastest one. If a 'fast' value is defined, then automatically, the /2 * one should be included as it can be used. Generally having more that * one fast set does not make sense, as static timings need to be changed diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c index a72476c24621..365b9435f748 100644 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ b/arch/arm/mach-pxa/corgi_lcd.c @@ -40,7 +40,7 @@ #define PICTRL_ADRS 0x06 #define POLCTRL_ADRS 0x07 -/* Resgister Bit Definitions */ +/* Register Bit Definitions */ #define RESCTL_QVGA 0x01 #define RESCTL_VGA 0x00 @@ -55,11 +55,11 @@ #define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ #define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ #define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ -#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */ +#define POWER0_COM_ON 0x08 /* COM Power Supply ON */ #define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ #define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ -#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */ +#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */ #define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ #define PICTRL_INIT_STATE 0x01 @@ -145,7 +145,7 @@ static void lcdtg_set_common_voltage(u8 base_data, u8 data) lcdtg_i2c_send_stop(base_data); } -/* Set Phase Adjuct */ +/* Set Phase Adjust */ static void lcdtg_set_phadadj(int mode) { int adj; @@ -226,7 +226,7 @@ static void lcdtg_hw_init(int mode) /* Signals output enable */ corgi_ssp_lcdtg_send(PICTRL_ADRS, 0); - /* Set Phase Adjuct */ + /* Set Phase Adjust */ lcdtg_set_phadadj(mode); /* Initialize for Input Signals from ATI */ diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index ff6b4ee037f5..40dea3d5142b 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c @@ -32,7 +32,7 @@ static struct corgissp_machinfo *ssp_machinfo; * There are three devices connected to the SSP interface: * 1. A touchscreen controller (TI ADS7846 compatible) * 2. An LCD contoller (with some Backlight functionality) - * 3. A battery moinitoring IC (Maxim MAX1111) + * 3. A battery monitoring IC (Maxim MAX1111) * * Each device uses a different speed/mode of communication. * diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index caf6b8bb6c95..c7bdf04ab094 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -30,7 +30,7 @@ static unsigned long mpcore_timer_rate; /* * local_timer_ack: checks for a local timer interrupt. * - * If a local timer interrupt has occured, acknowledge and return 1. + * If a local timer interrupt has occurred, acknowledge and return 1. * Otherwise, return 0. */ int local_timer_ack(void) diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 324f5a237921..4d6c7a574c1a 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -45,7 +45,7 @@ #include #include -/* onboard perihpheral map */ +/* onboard perihperal map */ static struct map_desc osiris_iodesc[] __initdata = { /* ISA IO areas (may be over-written later) */ diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 416e277054c2..29cb0c1604ab 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -25,7 +25,7 @@ static unsigned long __init sa1100_get_rtc_time(void) { /* * According to the manual we should be able to let RTTR be zero - * and then a default diviser for a 32.768KHz clock is used. + * and then a default divisor for a 32.768KHz clock is used. * Apparently this doesn't work, at least for my SA1110 rev 5. * If the clock divider is uninitialized then reset it to the * default value to get the 1Hz clock. diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 19ca333240ec..36440c899583 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -3,7 +3,7 @@ * * Copyright (C) 1995 Linus Torvalds * Modifications for ARM processor (c) 1995-2001 Russell King - * Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc. + * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc. * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. * Copyright (C) 1996, Cygnus Software Technologies Ltd. * diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index d6167ad4e011..f3ade18862aa 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -346,7 +346,7 @@ void __iounmap(volatile void __iomem *addr) #ifndef CONFIG_SMP /* * If this is a section based mapping we need to handle it - * specially as the VM subysystem does not know how to handle + * specially as the VM subsystem does not know how to handle * such a beast. We need the lock here b/c we need to clear * all the mappings before the area can be reclaimed * by someone else. diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 2ba1530d1ce1..02e050ae59f6 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -92,7 +92,7 @@ static struct cachepolicy cache_policies[] __initdata = { }; /* - * These are useful for identifing cache coherency + * These are useful for identifying cache coherency * problems by allowing the cache or the cache and * writebuffer to be turned off. (Note: the write * buffer should not be on and the cache off). diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index d3605934f1c7..c200c2810066 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -85,7 +85,7 @@ static int iop3xx_pci_status(void) /* * Simply write the address register and read the configuration - * data. Note that the 4 nop's ensure that we are able to handle + * data. Note that the 4 nops ensure that we are able to handle * a delayed abort (in theory.) */ static u32 iop3xx_read(unsigned long addr) diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index dd8708ad0a71..7987aa6e95f8 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -73,7 +73,7 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) } if (info != NULL) { /* Check the length as a lame attempt to check for - * binary inconsistancy. */ + * binary inconsistency. */ if (len != NO_LENGTH_CHECK) { /* Word-align len */ if (len & 0x03) diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 55a4d3be16b6..88d5b6d9f950 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1172,7 +1172,7 @@ static void set_b1_regs(void) break; default: BUG(); - return; /* Supress warning about uninitialized vars */ + return; /* Suppress warning about uninitialized vars */ } if (omap_dma_in_1510_mode()) { diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index bc46f33aede3..1f23f0459e5f 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -59,8 +59,8 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, /* * Depending on the target RAMFS firewall setup, the public usable amount of - * SRAM varies. The default accessable size for all device types is 2k. A GP - * device allows ARM11 but not other initators for full size. This + * SRAM varies. The default accessible size for all device types is 2k. A GP + * device allows ARM11 but not other initiators for full size. This * functionality seems ok until some nice security API happens. */ static int is_sram_locked(void) @@ -71,7 +71,7 @@ static int is_sram_locked(void) type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; if (type == GP_DEVICE) { - /* RAMFW: R/W access to all initators for all qualifier sets */ + /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index 25489aafb113..a5aedf964b88 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -177,7 +177,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) /* NOTE: SPEED and SUSP aren't configured here. OTG hosts * may be able to use I2C requests to set those bits along - * with VBUS switching and overcurrent detction. + * with VBUS switching and overcurrent detection. */ if (cpu_class_is_omap1() && nwires != 6) diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 6f03c9370979..08d80f2f51f2 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -1153,7 +1153,7 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); * * hwcfg: the value for xxxSTCn register, * bit 0: 0=increment pointer, 1=leave pointer - * bit 1: 0=soucre is AHB, 1=soucre is APB + * bit 1: 0=source is AHB, 1=source is APB * * devaddr: physical address of the source */ diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index c6b03f8ab260..5692eccdf4d1 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c @@ -555,7 +555,7 @@ static int s3c2410_pm_enter(suspend_state_t state) __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); - /* call cpu specific preperation */ + /* call cpu specific preparation */ pm_cpu_prep();