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MLK-24992-01 clk: imx8mp: Change system pll1/pll2 as fixed rate clock 

when system running at ND mode, the noc, noc_io & gic clock can be sourced
from system PLL1, then system PLL2 will be disable during boot stage. it
seems disabling system PLL2 will lead to system hang due to unknow reason.
As the system PLL1/PLL2 should be used as fixed rate PLL, so simplify the
complexity of clock tree management, change these two PLLs as fixed rate clock.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
zero-colors
Jacky Bai 2020-11-11 09:08:59 +08:00
parent 05d0b49db6
commit d15f256512
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/imx/clk-imx8mp.c
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@ -570,8 +570,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
clks[IMX8MP_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mp_gpu_pll);
clks[IMX8MP_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mp_vpu_pll);
clks[IMX8MP_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll);
clks[IMX8MP_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll);
clks[IMX8MP_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll);
clks[IMX8MP_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000);
clks[IMX8MP_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000);
clks[IMX8MP_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll);
/* PLL bypass out */