ARM: BCM5301X: add dts files for BCM4708 SoC
This uses the newly added BCM5301X SoC code. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Matt Porter <mporter@linaro.org>
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@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
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dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
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bcm28155-ap.dtb
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
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dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
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dtb-$(CONFIG_ARCH_BERLIN) += \
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berlin2-sony-nsz-gs7.dtb \
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berlin2cd-google-chromecast.dtb
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35
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
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35
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
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@ -0,0 +1,35 @@
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/*
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* Broadcom BCM470X / BCM5301X arm platform code.
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* DTS for Netgear R6250 V1
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*
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* Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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/dts-v1/;
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#include "bcm4708.dtsi"
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/ {
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compatible = "netgear,r6250v1", "brcm,bcm4708";
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model = "Netgear R6250 V1 (BCM4708)";
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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memory {
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reg = <0x00000000 0x08000000>;
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};
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chipcommonA {
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uart0: serial@0300 {
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status = "okay";
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};
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uart1: serial@0400 {
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status = "okay";
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};
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};
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};
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34
arch/arm/boot/dts/bcm4708.dtsi
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34
arch/arm/boot/dts/bcm4708.dtsi
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@ -0,0 +1,34 @@
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/*
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* Broadcom BCM470X / BCM5301X ARM platform code.
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* DTS for BCM4708 SoC.
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*
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* Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcm5301x.dtsi"
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/ {
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compatible = "brcm,bcm4708";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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};
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};
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95
arch/arm/boot/dts/bcm5301x.dtsi
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95
arch/arm/boot/dts/bcm5301x.dtsi
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@ -0,0 +1,95 @@
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/*
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* Broadcom BCM470X / BCM5301X ARM platform code.
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* Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
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* BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
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*
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* Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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chipcommonA {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18000000 0x00001000>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@0300 {
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compatible = "ns16550";
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reg = <0x0300 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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uart1: serial@0400 {
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compatible = "ns16550";
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reg = <0x0400 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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};
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mpcore {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19020000 0x00003000>;
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#address-cells = <1>;
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#size-cells = <1>;
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scu@0000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x0000 0x100>;
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};
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timer@0200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x0200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_periph>;
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};
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local-timer@0600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x0600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_periph>;
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};
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x0100 0x100>;
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};
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L2: cache-controller@2000 {
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compatible = "arm,pl310-cache";
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reg = <0x2000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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/* As long as we do not have a real clock driver us this
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* fixed clock */
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clk_periph: periph {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <400000000>;
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};
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};
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};
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