powerpc: Don't corrupt transactional state when using FP/VMX in kernel
Currently, when we have a process using the transactional memory
facilities on POWER8 (that is, the processor is in transactional
or suspended state), and the process enters the kernel and the
kernel then uses the floating-point or vector (VMX/Altivec) facility,
we end up corrupting the user-visible FP/VMX/VSX state. This
happens, for example, if a page fault causes a copy-on-write
operation, because the copy_page function will use VMX to do the
copy on POWER8. The test program below demonstrates the bug.
The bug happens because when FP/VMX state for a transactional process
is stored in the thread_struct, we store the checkpointed state in
.fp_state/.vr_state and the transactional (current) state in
.transact_fp/.transact_vr. However, when the kernel wants to use
FP/VMX, it calls enable_kernel_fp() or enable_kernel_altivec(),
which saves the current state in .fp_state/.vr_state. Furthermore,
when we return to the user process we return with FP/VMX/VSX
disabled. The next time the process uses FP/VMX/VSX, we don't know
which set of state (the current register values, .fp_state/.vr_state,
or .transact_fp/.transact_vr) we should be using, since we have no
way to tell if we are still in the same transaction, and if not,
whether the previous transaction succeeded or failed.
Thus it is necessary to strictly adhere to the rule that if FP has
been enabled at any point in a transaction, we must keep FP enabled
for the user process with the current transactional state in the
FP registers, until we detect that it is no longer in a transaction.
Similarly for VMX; once enabled it must stay enabled until the
process is no longer transactional.
In order to keep this rule, we add a new thread_info flag which we
test when returning from the kernel to userspace, called TIF_RESTORE_TM.
This flag indicates that there is FP/VMX/VSX state to be restored
before entering userspace, and when it is set the .tm_orig_msr field
in the thread_struct indicates what state needs to be restored.
The restoration is done by restore_tm_state(). The TIF_RESTORE_TM
bit is set by new giveup_fpu/altivec_maybe_transactional helpers,
which are called from enable_kernel_fp/altivec, giveup_vsx, and
flush_fp/altivec_to_thread instead of giveup_fpu/altivec.
The other thing to be done is to get the transactional FP/VMX/VSX
state from .fp_state/.vr_state when doing reclaim, if that state
has been saved there by giveup_fpu/altivec_maybe_transactional.
Having done this, we set the FP/VMX bit in the thread's MSR after
reclaim to indicate that that part of the state is now valid
(having been reclaimed from the processor's checkpointed state).
Finally, in the signal handling code, we move the clearing of the
transactional state bits in the thread's MSR a bit earlier, before
calling flush_fp_to_thread(), so that we don't unnecessarily set
the TIF_RESTORE_TM bit.
This is the test program:
/* Michael Neuling 4/12/2013
*
* See if the altivec state is leaked out of an aborted transaction due to
* kernel vmx copy loops.
*
* gcc -m64 htm_vmxcopy.c -o htm_vmxcopy
*
*/
/* We don't use all of these, but for reference: */
int main(int argc, char *argv[])
{
long double vecin = 1.3;
long double vecout;
unsigned long pgsize = getpagesize();
int i;
int fd;
int size = pgsize*16;
char tmpfile[] = "/tmp/page_faultXXXXXX";
char buf[pgsize];
char *a;
uint64_t aborted = 0;
fd = mkstemp(tmpfile);
assert(fd >= 0);
memset(buf, 0, pgsize);
for (i = 0; i < size; i += pgsize)
assert(write(fd, buf, pgsize) == pgsize);
unlink(tmpfile);
a = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
assert(a != MAP_FAILED);
asm __volatile__(
"lxvd2x 40,0,%[vecinptr] ; " // set 40 to initial value
TBEGIN
"beq 3f ;"
TSUSPEND
"xxlxor 40,40,40 ; " // set 40 to 0
"std 5, 0(%[map]) ;" // cause kernel vmx copy page
TABORT
TRESUME
TEND
"li %[res], 0 ;"
"b 5f ;"
"3: ;" // Abort handler
"li %[res], 1 ;"
"5: ;"
"stxvd2x 40,0,%[vecoutptr] ; "
: [res]"=r"(aborted)
: [vecinptr]"r"(&vecin),
[vecoutptr]"r"(&vecout),
[map]"r"(a)
: "memory", "r0", "r3", "r4", "r5", "r6", "r7");
if (aborted && (vecin != vecout)){
printf("FAILED: vector state leaked on abort %f != %f\n",
(double)vecin, (double)vecout);
exit(1);
}
munmap(a, size);
close(fd);
printf("PASSED!\n");
return 0;
}
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Paul Mackerras
Benjamin Herrenschmidt
parent
ae39c58c2e
commit
d31626f70b
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@ -373,6 +373,8 @@ extern int set_endian(struct task_struct *tsk, unsigned int val);
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extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
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extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
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extern void fp_enable(void);
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extern void vec_enable(void);
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extern void load_fp_state(struct thread_fp_state *fp);
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extern void store_fp_state(struct thread_fp_state *fp);
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extern void load_vr_state(struct thread_vr_state *vr);
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@ -91,6 +91,7 @@ static inline struct thread_info *current_thread_info(void)
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#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
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TIF_NEED_RESCHED */
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#define TIF_32BIT 4 /* 32 bit binary */
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#define TIF_RESTORE_TM 5 /* need to restore TM FP/VEC/VSX */
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#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
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#define TIF_SINGLESTEP 8 /* singlestepping active */
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#define TIF_NOHZ 9 /* in adaptive nohz mode */
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@ -113,6 +114,7 @@ static inline struct thread_info *current_thread_info(void)
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#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
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#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
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#define _TIF_32BIT (1<<TIF_32BIT)
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#define _TIF_RESTORE_TM (1<<TIF_RESTORE_TM)
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#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
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#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
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#define _TIF_SECCOMP (1<<TIF_SECCOMP)
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@ -128,7 +130,8 @@ static inline struct thread_info *current_thread_info(void)
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_TIF_NOHZ)
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#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
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_TIF_NOTIFY_RESUME | _TIF_UPROBE)
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_TIF_NOTIFY_RESUME | _TIF_UPROBE | \
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_TIF_RESTORE_TM)
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#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR)
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/* Bits in local_flags */
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@ -15,6 +15,7 @@ extern void do_load_up_transact_altivec(struct thread_struct *thread);
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extern void tm_enable(void);
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extern void tm_reclaim(struct thread_struct *thread,
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unsigned long orig_msr, uint8_t cause);
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extern void tm_reclaim_current(uint8_t cause);
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extern void tm_recheckpoint(struct thread_struct *thread,
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unsigned long orig_msr);
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extern void tm_abort(uint8_t cause);
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@ -664,8 +664,16 @@ _GLOBAL(ret_from_except_lite)
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bl .restore_interrupts
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SCHEDULE_USER
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b .ret_from_except_lite
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2: bl .save_nvgprs
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2:
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
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bne 3f /* only restore TM if nothing else to do */
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl .restore_tm_state
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b restore
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3:
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#endif
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bl .save_nvgprs
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bl .restore_interrupts
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl .do_notify_resume
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@ -80,6 +80,22 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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blr
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
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/*
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* Enable use of the FPU, and VSX if possible, for the caller.
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*/
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_GLOBAL(fp_enable)
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mfmsr r3
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ori r3,r3,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r3,r3,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC
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MTMSRD(r3)
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isync /* (not necessary for arch 2.02 and later) */
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blr
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/*
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* Load state from memory into FP registers including FPSCR.
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* Assumes the caller has enabled FP in the MSR.
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@ -73,6 +73,48 @@ struct task_struct *last_task_used_vsx = NULL;
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struct task_struct *last_task_used_spe = NULL;
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#endif
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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void giveup_fpu_maybe_transactional(struct task_struct *tsk)
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{
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/*
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* If we are saving the current thread's registers, and the
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* thread is in a transactional state, set the TIF_RESTORE_TM
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* bit so that we know to restore the registers before
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* returning to userspace.
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*/
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if (tsk == current && tsk->thread.regs &&
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MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
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!test_thread_flag(TIF_RESTORE_TM)) {
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tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
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set_thread_flag(TIF_RESTORE_TM);
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}
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giveup_fpu(tsk);
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}
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void giveup_altivec_maybe_transactional(struct task_struct *tsk)
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{
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/*
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* If we are saving the current thread's registers, and the
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* thread is in a transactional state, set the TIF_RESTORE_TM
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* bit so that we know to restore the registers before
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* returning to userspace.
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*/
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if (tsk == current && tsk->thread.regs &&
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MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
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!test_thread_flag(TIF_RESTORE_TM)) {
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tsk->thread.tm_orig_msr = tsk->thread.regs->msr;
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set_thread_flag(TIF_RESTORE_TM);
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}
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giveup_altivec(tsk);
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}
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#else
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#define giveup_fpu_maybe_transactional(tsk) giveup_fpu(tsk)
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#define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
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#ifdef CONFIG_PPC_FPU
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/*
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* Make sure the floating-point register state in the
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@ -101,13 +143,13 @@ void flush_fp_to_thread(struct task_struct *tsk)
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*/
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BUG_ON(tsk != current);
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#endif
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giveup_fpu(tsk);
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giveup_fpu_maybe_transactional(tsk);
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}
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preempt_enable();
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}
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}
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EXPORT_SYMBOL_GPL(flush_fp_to_thread);
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#endif
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#endif /* CONFIG_PPC_FPU */
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void enable_kernel_fp(void)
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{
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@ -115,11 +157,11 @@ void enable_kernel_fp(void)
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#ifdef CONFIG_SMP
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if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
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giveup_fpu(current);
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giveup_fpu_maybe_transactional(current);
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else
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giveup_fpu(NULL); /* just enables FP for kernel */
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#else
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giveup_fpu(last_task_used_math);
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giveup_fpu_maybe_transactional(last_task_used_math);
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#endif /* CONFIG_SMP */
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}
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EXPORT_SYMBOL(enable_kernel_fp);
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@ -131,11 +173,11 @@ void enable_kernel_altivec(void)
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#ifdef CONFIG_SMP
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if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
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giveup_altivec(current);
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giveup_altivec_maybe_transactional(current);
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else
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giveup_altivec_notask();
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#else
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giveup_altivec(last_task_used_altivec);
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giveup_altivec_maybe_transactional(last_task_used_altivec);
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#endif /* CONFIG_SMP */
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}
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EXPORT_SYMBOL(enable_kernel_altivec);
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@ -152,7 +194,7 @@ void flush_altivec_to_thread(struct task_struct *tsk)
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#ifdef CONFIG_SMP
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BUG_ON(tsk != current);
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#endif
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giveup_altivec(tsk);
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giveup_altivec_maybe_transactional(tsk);
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}
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preempt_enable();
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}
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@ -181,8 +223,8 @@ EXPORT_SYMBOL(enable_kernel_vsx);
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void giveup_vsx(struct task_struct *tsk)
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{
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giveup_fpu(tsk);
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giveup_altivec(tsk);
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giveup_fpu_maybe_transactional(tsk);
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giveup_altivec_maybe_transactional(tsk);
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__giveup_vsx(tsk);
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}
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@ -478,7 +520,48 @@ static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
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return false;
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return true;
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}
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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static void tm_reclaim_thread(struct thread_struct *thr,
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struct thread_info *ti, uint8_t cause)
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{
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unsigned long msr_diff = 0;
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/*
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* If FP/VSX registers have been already saved to the
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* thread_struct, move them to the transact_fp array.
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* We clear the TIF_RESTORE_TM bit since after the reclaim
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* the thread will no longer be transactional.
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*/
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if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
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msr_diff = thr->tm_orig_msr & ~thr->regs->msr;
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if (msr_diff & MSR_FP)
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memcpy(&thr->transact_fp, &thr->fp_state,
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sizeof(struct thread_fp_state));
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if (msr_diff & MSR_VEC)
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memcpy(&thr->transact_vr, &thr->vr_state,
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sizeof(struct thread_vr_state));
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clear_ti_thread_flag(ti, TIF_RESTORE_TM);
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msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
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}
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tm_reclaim(thr, thr->regs->msr, cause);
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/* Having done the reclaim, we now have the checkpointed
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* FP/VSX values in the registers. These might be valid
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* even if we have previously called enable_kernel_fp() or
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* flush_fp_to_thread(), so update thr->regs->msr to
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* indicate their current validity.
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*/
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thr->regs->msr |= msr_diff;
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}
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void tm_reclaim_current(uint8_t cause)
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{
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tm_enable();
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tm_reclaim_thread(¤t->thread, current_thread_info(), cause);
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}
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static inline void tm_reclaim_task(struct task_struct *tsk)
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{
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/* We have to work out if we're switching from/to a task that's in the
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@ -501,9 +584,11 @@ static inline void tm_reclaim_task(struct task_struct *tsk)
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/* Stash the original thread MSR, as giveup_fpu et al will
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* modify it. We hold onto it to see whether the task used
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* FP & vector regs.
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* FP & vector regs. If the TIF_RESTORE_TM flag is set,
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* tm_orig_msr is already set.
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*/
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thr->tm_orig_msr = thr->regs->msr;
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if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
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thr->tm_orig_msr = thr->regs->msr;
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TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
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"ccr=%lx, msr=%lx, trap=%lx)\n",
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@ -511,7 +596,7 @@ static inline void tm_reclaim_task(struct task_struct *tsk)
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thr->regs->ccr, thr->regs->msr,
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thr->regs->trap);
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tm_reclaim(thr, thr->regs->msr, TM_CAUSE_RESCHED);
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tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
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TM_DEBUG("--- tm_reclaim on pid %d complete\n",
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tsk->pid);
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@ -587,6 +672,43 @@ static inline void __switch_to_tm(struct task_struct *prev)
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tm_reclaim_task(prev);
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}
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}
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/*
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* This is called if we are on the way out to userspace and the
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* TIF_RESTORE_TM flag is set. It checks if we need to reload
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* FP and/or vector state and does so if necessary.
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* If userspace is inside a transaction (whether active or
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* suspended) and FP/VMX/VSX instructions have ever been enabled
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* inside that transaction, then we have to keep them enabled
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* and keep the FP/VMX/VSX state loaded while ever the transaction
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* continues. The reason is that if we didn't, and subsequently
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* got a FP/VMX/VSX unavailable interrupt inside a transaction,
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* we don't know whether it's the same transaction, and thus we
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* don't know which of the checkpointed state and the transactional
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* state to use.
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*/
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void restore_tm_state(struct pt_regs *regs)
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{
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unsigned long msr_diff;
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clear_thread_flag(TIF_RESTORE_TM);
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if (!MSR_TM_ACTIVE(regs->msr))
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return;
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msr_diff = current->thread.tm_orig_msr & ~regs->msr;
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msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
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if (msr_diff & MSR_FP) {
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fp_enable();
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load_fp_state(¤t->thread.fp_state);
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regs->msr |= current->thread.fpexc_mode;
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}
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if (msr_diff & MSR_VEC) {
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vec_enable();
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load_vr_state(¤t->thread.vr_state);
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}
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regs->msr |= msr_diff;
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}
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#else
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#define tm_recheckpoint_new_task(new)
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#define __switch_to_tm(prev)
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@ -203,8 +203,7 @@ unsigned long get_tm_stackpointer(struct pt_regs *regs)
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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if (MSR_TM_ACTIVE(regs->msr)) {
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tm_enable();
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tm_reclaim(¤t->thread, regs->msr, TM_CAUSE_SIGNAL);
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tm_reclaim_current(TM_CAUSE_SIGNAL);
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if (MSR_TM_TRANSACTIONAL(regs->msr))
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return current->thread.ckpt_regs.gpr[1];
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}
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@ -519,6 +519,13 @@ static int save_tm_user_regs(struct pt_regs *regs,
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{
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unsigned long msr = regs->msr;
|
||||
|
||||
/* Remove TM bits from thread's MSR. The MSR in the sigcontext
|
||||
* just indicates to userland that we were doing a transaction, but we
|
||||
* don't want to return in transactional state. This also ensures
|
||||
* that flush_fp_to_thread won't set TIF_RESTORE_TM again.
|
||||
*/
|
||||
regs->msr &= ~MSR_TS_MASK;
|
||||
|
||||
/* Make sure floating point registers are stored in regs */
|
||||
flush_fp_to_thread(current);
|
||||
|
||||
|
|
@ -1056,13 +1063,6 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
|
|||
/* enter the signal handler in native-endian mode */
|
||||
regs->msr &= ~MSR_LE;
|
||||
regs->msr |= (MSR_KERNEL & MSR_LE);
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
/* Remove TM bits from thread's MSR. The MSR in the sigcontext
|
||||
* just indicates to userland that we were doing a transaction, but we
|
||||
* don't want to return in transactional state:
|
||||
*/
|
||||
regs->msr &= ~MSR_TS_MASK;
|
||||
#endif
|
||||
return 1;
|
||||
|
||||
badframe:
|
||||
|
|
@ -1484,13 +1484,6 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
|
|||
regs->nip = (unsigned long) ka->sa.sa_handler;
|
||||
/* enter the signal handler in big-endian mode */
|
||||
regs->msr &= ~MSR_LE;
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
/* Remove TM bits from thread's MSR. The MSR in the sigcontext
|
||||
* just indicates to userland that we were doing a transaction, but we
|
||||
* don't want to return in transactional state:
|
||||
*/
|
||||
regs->msr &= ~MSR_TS_MASK;
|
||||
#endif
|
||||
return 1;
|
||||
|
||||
badframe:
|
||||
|
|
|
|||
|
|
@ -192,6 +192,13 @@ static long setup_tm_sigcontexts(struct sigcontext __user *sc,
|
|||
|
||||
BUG_ON(!MSR_TM_ACTIVE(regs->msr));
|
||||
|
||||
/* Remove TM bits from thread's MSR. The MSR in the sigcontext
|
||||
* just indicates to userland that we were doing a transaction, but we
|
||||
* don't want to return in transactional state. This also ensures
|
||||
* that flush_fp_to_thread won't set TIF_RESTORE_TM again.
|
||||
*/
|
||||
regs->msr &= ~MSR_TS_MASK;
|
||||
|
||||
flush_fp_to_thread(current);
|
||||
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
|
|
@ -749,13 +756,6 @@ int handle_rt_signal64(int signr, struct k_sigaction *ka, siginfo_t *info,
|
|||
|
||||
/* Make sure signal handler doesn't get spurious FP exceptions */
|
||||
current->thread.fp_state.fpscr = 0;
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
/* Remove TM bits from thread's MSR. The MSR in the sigcontext
|
||||
* just indicates to userland that we were doing a transaction, but we
|
||||
* don't want to return in transactional state:
|
||||
*/
|
||||
regs->msr &= ~MSR_TS_MASK;
|
||||
#endif
|
||||
|
||||
/* Set up to return from userspace. */
|
||||
if (vdso64_rt_sigtramp && current->mm->context.vdso_base) {
|
||||
|
|
|
|||
|
|
@ -1399,7 +1399,6 @@ void fp_unavailable_tm(struct pt_regs *regs)
|
|||
|
||||
TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
|
||||
regs->nip, regs->msr);
|
||||
tm_enable();
|
||||
|
||||
/* We can only have got here if the task started using FP after
|
||||
* beginning the transaction. So, the transactional regs are just a
|
||||
|
|
@ -1408,8 +1407,7 @@ void fp_unavailable_tm(struct pt_regs *regs)
|
|||
* transaction, and probably retry but now with FP enabled. So the
|
||||
* checkpointed FP registers need to be loaded.
|
||||
*/
|
||||
tm_reclaim(¤t->thread, current->thread.regs->msr,
|
||||
TM_CAUSE_FAC_UNAV);
|
||||
tm_reclaim_current(TM_CAUSE_FAC_UNAV);
|
||||
/* Reclaim didn't save out any FPRs to transact_fprs. */
|
||||
|
||||
/* Enable FP for the task: */
|
||||
|
|
@ -1432,9 +1430,7 @@ void altivec_unavailable_tm(struct pt_regs *regs)
|
|||
TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
|
||||
"MSR=%lx\n",
|
||||
regs->nip, regs->msr);
|
||||
tm_enable();
|
||||
tm_reclaim(¤t->thread, current->thread.regs->msr,
|
||||
TM_CAUSE_FAC_UNAV);
|
||||
tm_reclaim_current(TM_CAUSE_FAC_UNAV);
|
||||
regs->msr |= MSR_VEC;
|
||||
tm_recheckpoint(¤t->thread, regs->msr);
|
||||
current->thread.used_vr = 1;
|
||||
|
|
@ -1455,10 +1451,8 @@ void vsx_unavailable_tm(struct pt_regs *regs)
|
|||
"MSR=%lx\n",
|
||||
regs->nip, regs->msr);
|
||||
|
||||
tm_enable();
|
||||
/* This reclaims FP and/or VR regs if they're already enabled */
|
||||
tm_reclaim(¤t->thread, current->thread.regs->msr,
|
||||
TM_CAUSE_FAC_UNAV);
|
||||
tm_reclaim_current(TM_CAUSE_FAC_UNAV);
|
||||
|
||||
regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
|
||||
MSR_VSX;
|
||||
|
|
|
|||
|
|
@ -36,6 +36,16 @@ _GLOBAL(do_load_up_transact_altivec)
|
|||
blr
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enable use of VMX/Altivec for the caller.
|
||||
*/
|
||||
_GLOBAL(vec_enable)
|
||||
mfmsr r3
|
||||
oris r3,r3,MSR_VEC@h
|
||||
MTMSRD(r3)
|
||||
isync
|
||||
blr
|
||||
|
||||
/*
|
||||
* Load state from memory into VMX registers including VSCR.
|
||||
* Assumes the caller has enabled VMX in the MSR.
|
||||
|
|
|
|||
Loading…
Reference in a new issue