nvidiafb/rivafb: switch to pci_get refcounting
Switch to pci_get refcounting APIs [adaplas] Fix a long-standing bug where the return value of pci_find_slot()/pci_get_bus_and_slot() is ignored. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -686,7 +686,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
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if ((par->Chipset & 0x0FF0) == 0x01A0) {
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unsigned int uMClkPostDiv;
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dev = pci_find_slot(0, 3);
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dev = pci_get_bus_and_slot(0, 3);
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pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
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uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
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@ -694,11 +694,11 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
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uMClkPostDiv = 4;
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MClk = 400000 / uMClkPostDiv;
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} else {
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dev = pci_find_slot(0, 5);
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dev = pci_get_bus_and_slot(0, 5);
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pci_read_config_dword(dev, 0x4c, &MClk);
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MClk /= 1000;
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}
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pci_dev_put(dev);
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pll = NV_RD32(par->PRAMDAC0, 0x0500);
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M = (pll >> 0) & 0xFF;
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N = (pll >> 8) & 0xFF;
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@ -707,19 +707,21 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
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sim_data.pix_bpp = (char)pixelDepth;
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sim_data.enable_video = 0;
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sim_data.enable_mp = 0;
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pci_find_slot(0, 1);
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dev = pci_get_bus_and_slot(0, 1);
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pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
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pci_dev_put(dev);
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sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
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sim_data.memory_width = 64;
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dev = pci_find_slot(0, 3);
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dev = pci_get_bus_and_slot(0, 3);
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pci_read_config_dword(dev, 0, &memctrl);
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pci_dev_put(dev);
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memctrl >>= 16;
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if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
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int dimm[3];
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pci_find_slot(0, 2);
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dev = pci_get_bus_and_slot(0, 2);
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pci_read_config_dword(dev, 0x40, &dimm[0]);
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dimm[0] = (dimm[0] >> 8) & 0x4f;
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pci_read_config_dword(dev, 0x44, &dimm[1]);
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@ -731,6 +733,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
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printk("nvidiafb: your nForce DIMMs are not arranged "
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"in optimal banks!\n");
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}
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pci_dev_put(dev);
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}
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sim_data.mem_latency = 3;
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@ -261,7 +261,7 @@ static void nv10GetConfig(struct nvidia_par *par)
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}
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#endif
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dev = pci_find_slot(0, 1);
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dev = pci_get_bus_and_slot(0, 1);
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if ((par->Chipset & 0xffff) == 0x01a0) {
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int amt = 0;
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@ -276,6 +276,7 @@ static void nv10GetConfig(struct nvidia_par *par)
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par->RamAmountKBytes =
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(NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
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}
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pci_dev_put(dev);
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par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
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14318 : 13500;
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@ -231,12 +231,14 @@ unsigned long riva_get_memlen(struct riva_par *par)
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case NV_ARCH_30:
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if(chipset == NV_CHIP_IGEFORCE2) {
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dev = pci_find_slot(0, 1);
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dev = pci_get_bus_and_slot(0, 1);
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pci_read_config_dword(dev, 0x7C, &amt);
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pci_dev_put(dev);
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memlen = (((amt >> 6) & 31) + 1) * 1024;
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} else if (chipset == NV_CHIP_0x01F0) {
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dev = pci_find_slot(0, 1);
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dev = pci_get_bus_and_slot(0, 1);
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pci_read_config_dword(dev, 0x84, &amt);
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pci_dev_put(dev);
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memlen = (((amt >> 4) & 127) + 1) * 1024;
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} else {
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switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) &
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@ -1118,8 +1118,9 @@ static void nForceUpdateArbitrationSettings
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unsigned int uMClkPostDiv;
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struct pci_dev *dev;
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dev = pci_find_slot(0, 3);
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dev = pci_get_bus_and_slot(0, 3);
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pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
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pci_dev_put(dev);
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uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
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if(!uMClkPostDiv) uMClkPostDiv = 4;
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@ -1132,8 +1133,9 @@ static void nForceUpdateArbitrationSettings
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sim_data.enable_video = 0;
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sim_data.enable_mp = 0;
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dev = pci_find_slot(0, 1);
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dev = pci_get_bus_and_slot(0, 1);
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pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
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pci_dev_put(dev);
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sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
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sim_data.memory_width = 64;
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@ -2112,12 +2114,14 @@ static void nv10GetConfig
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* Fill in chip configuration.
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*/
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if(chipset == NV_CHIP_IGEFORCE2) {
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dev = pci_find_slot(0, 1);
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dev = pci_get_bus_and_slot(0, 1);
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pci_read_config_dword(dev, 0x7C, &amt);
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pci_dev_put(dev);
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chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
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} else if(chipset == NV_CHIP_0x01F0) {
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dev = pci_find_slot(0, 1);
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dev = pci_get_bus_and_slot(0, 1);
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pci_read_config_dword(dev, 0x84, &amt);
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pci_dev_put(dev);
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chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
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} else {
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switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)
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