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ARM: SoC: late fixes and dependencies 

This is a collection of a few late fixes and other misc. stuff that
 had dependencies on things being merged from other trees.
 
 Other than the fixes, the primary feature being added is the
 conversion of some OMAP drivers to the new generic wakeirq interface.
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late fixes and dependencies from Kevin Hilman:
 "This is a collection of a few late fixes and other misc stuff that had
  dependencies on things being merged from other trees.

  Other than the fixes, the primary feature being added is the
  conversion of some OMAP drivers to the new generic wakeirq interface"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: multi_v7_defconfig: Enable BRCMNAND driver
  ARM: BCM: Do not select CONFIG_MTD_NAND_BRCMNAND
  ARM: at91/dt: update udc compatible strings
  ARM: at91/dt: trivial: fix USB udc compatible string
  arm64: dts: Add APM X-Gene standby GPIO controller DTS entries
  soc: qcom: spm: Fix idle on THUMB2 kernels
  ARM: dove: fix legacy dove IRQ numbers
  ARM: mvebu: fix suspend to RAM on big-endian configurations
  ARM: mvebu: adjust Armada XP DT spi muxing after pinctrl function rename
  serial: 8250_omap: Move wake-up interrupt to generic wakeirq
  serial: omap: Switch wake-up interrupt to generic wakeirq
  mmc: omap_hsmmc: Change wake-up interrupt to use generic wakeirq
steinar/wifi_calib_4_9_kernel
Linus Torvalds 2015-07-02 14:40:49 -07:00
parent 848077270d ae41a0b7ed
commit d4113f2f17
16 changed files with 103 additions and 201 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/usb/atmel-usb.txt
View File

@ -79,9 +79,9 @@ Atmel High-Speed USB device controller
Required properties:
- compatible: Should be one of the following
"at91sam9rl-udc"
"at91sam9g45-udc"
"sama5d3-udc"
"atmel,at91sam9rl-udc"
"atmel,at91sam9g45-udc"
"atmel,sama5d3-udc"
- reg: Address and length of the register set for the device
- interrupts: Should contain usba interrupt
- clocks: Should reference the peripheral and host clocks

2
arch/arm/boot/dts/armada-xp.dtsi
View File

@ -305,7 +305,7 @@
spi0_pins: spi0-pins {
marvell,pins = "mpp36", "mpp37",
"mpp38", "mpp39";
marvell,function = "spi";
marvell,function = "spi0";
};
uart2_pins: uart2-pins {

2
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -1148,7 +1148,7 @@
usb2: gadget@fff78000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9rl-udc";
compatible = "atmel,at91sam9g45-udc";
reg = <0x00600000 0x80000
0xfff78000 0x400>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;

2
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -1108,7 +1108,7 @@
usb2: gadget@f803c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9rl-udc";
compatible = "atmel,at91sam9g45-udc";
reg = <0x00500000 0x80000
0xf803c000 0x400>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;

2
arch/arm/boot/dts/sama5d3.dtsi
View File

@ -1321,7 +1321,7 @@
usb0: gadget@00500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9rl-udc";
compatible = "atmel,sama5d3-udc";
reg = <0x00500000 0x100000
0xf8030000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;

2
arch/arm/boot/dts/sama5d4.dtsi
View File

@ -127,7 +127,7 @@
usb0: gadget@00400000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9rl-udc";
compatible = "atmel,sama5d3-udc";
reg = <0x00400000 0x100000
0xfc02c000 0x4000>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;

1
arch/arm/configs/multi_v7_defconfig
View File

@ -169,6 +169,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_BRCMNAND=y
CONFIG_MTD_NAND_DAVINCI=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y

1
arch/arm/mach-bcm/Kconfig
View File

@ -19,7 +19,6 @@ config ARCH_BCM_IPROC
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select PINCTRL
select MTD_NAND_BRCMNAND
help
This enables support for systems based on Broadcom IPROC architected SoCs.
The IPROC complex contains one or more ARM CPUs along with common

118
arch/arm/mach-dove/include/mach/irqs.h
View File

@ -14,73 +14,73 @@
/*
* Dove Low Interrupt Controller
*/
#define IRQ_DOVE_BRIDGE 0
#define IRQ_DOVE_H2C 1
#define IRQ_DOVE_C2H 2
#define IRQ_DOVE_NAND 3
#define IRQ_DOVE_PDMA 4
#define IRQ_DOVE_SPI1 5
#define IRQ_DOVE_SPI0 6
#define IRQ_DOVE_UART_0 7
#define IRQ_DOVE_UART_1 8
#define IRQ_DOVE_UART_2 9
#define IRQ_DOVE_UART_3 10
#define IRQ_DOVE_I2C 11
#define IRQ_DOVE_GPIO_0_7 12
#define IRQ_DOVE_GPIO_8_15 13
#define IRQ_DOVE_GPIO_16_23 14
#define IRQ_DOVE_PCIE0_ERR 15
#define IRQ_DOVE_PCIE0 16
#define IRQ_DOVE_PCIE1_ERR 17
#define IRQ_DOVE_PCIE1 18
#define IRQ_DOVE_I2S0 19
#define IRQ_DOVE_I2S0_ERR 20
#define IRQ_DOVE_I2S1 21
#define IRQ_DOVE_I2S1_ERR 22
#define IRQ_DOVE_USB_ERR 23
#define IRQ_DOVE_USB0 24
#define IRQ_DOVE_USB1 25
#define IRQ_DOVE_GE00_RX 26
#define IRQ_DOVE_GE00_TX 27
#define IRQ_DOVE_GE00_MISC 28
#define IRQ_DOVE_GE00_SUM 29
#define IRQ_DOVE_GE00_ERR 30
#define IRQ_DOVE_CRYPTO 31
#define IRQ_DOVE_BRIDGE (1 + 0)
#define IRQ_DOVE_H2C (1 + 1)
#define IRQ_DOVE_C2H (1 + 2)
#define IRQ_DOVE_NAND (1 + 3)
#define IRQ_DOVE_PDMA (1 + 4)
#define IRQ_DOVE_SPI1 (1 + 5)
#define IRQ_DOVE_SPI0 (1 + 6)
#define IRQ_DOVE_UART_0 (1 + 7)
#define IRQ_DOVE_UART_1 (1 + 8)
#define IRQ_DOVE_UART_2 (1 + 9)
#define IRQ_DOVE_UART_3 (1 + 10)
#define IRQ_DOVE_I2C (1 + 11)
#define IRQ_DOVE_GPIO_0_7 (1 + 12)
#define IRQ_DOVE_GPIO_8_15 (1 + 13)
#define IRQ_DOVE_GPIO_16_23 (1 + 14)
#define IRQ_DOVE_PCIE0_ERR (1 + 15)
#define IRQ_DOVE_PCIE0 (1 + 16)
#define IRQ_DOVE_PCIE1_ERR (1 + 17)
#define IRQ_DOVE_PCIE1 (1 + 18)
#define IRQ_DOVE_I2S0 (1 + 19)
#define IRQ_DOVE_I2S0_ERR (1 + 20)
#define IRQ_DOVE_I2S1 (1 + 21)
#define IRQ_DOVE_I2S1_ERR (1 + 22)
#define IRQ_DOVE_USB_ERR (1 + 23)
#define IRQ_DOVE_USB0 (1 + 24)
#define IRQ_DOVE_USB1 (1 + 25)
#define IRQ_DOVE_GE00_RX (1 + 26)
#define IRQ_DOVE_GE00_TX (1 + 27)
#define IRQ_DOVE_GE00_MISC (1 + 28)
#define IRQ_DOVE_GE00_SUM (1 + 29)
#define IRQ_DOVE_GE00_ERR (1 + 30)
#define IRQ_DOVE_CRYPTO (1 + 31)
/*
* Dove High Interrupt Controller
*/
#define IRQ_DOVE_AC97 32
#define IRQ_DOVE_PMU 33
#define IRQ_DOVE_CAM 34
#define IRQ_DOVE_SDIO0 35
#define IRQ_DOVE_SDIO1 36
#define IRQ_DOVE_SDIO0_WAKEUP 37
#define IRQ_DOVE_SDIO1_WAKEUP 38
#define IRQ_DOVE_XOR_00 39
#define IRQ_DOVE_XOR_01 40
#define IRQ_DOVE_XOR0_ERR 41
#define IRQ_DOVE_XOR_10 42
#define IRQ_DOVE_XOR_11 43
#define IRQ_DOVE_XOR1_ERR 44
#define IRQ_DOVE_LCD_DCON 45
#define IRQ_DOVE_LCD1 46
#define IRQ_DOVE_LCD0 47
#define IRQ_DOVE_GPU 48
#define IRQ_DOVE_PERFORM_MNTR 49
#define IRQ_DOVE_VPRO_DMA1 51
#define IRQ_DOVE_SSP_TIMER 54
#define IRQ_DOVE_SSP 55
#define IRQ_DOVE_MC_L2_ERR 56
#define IRQ_DOVE_CRYPTO_ERR 59
#define IRQ_DOVE_GPIO_24_31 60
#define IRQ_DOVE_HIGH_GPIO 61
#define IRQ_DOVE_SATA 62
#define IRQ_DOVE_AC97 (1 + 32)
#define IRQ_DOVE_PMU (1 + 33)
#define IRQ_DOVE_CAM (1 + 34)
#define IRQ_DOVE_SDIO0 (1 + 35)
#define IRQ_DOVE_SDIO1 (1 + 36)
#define IRQ_DOVE_SDIO0_WAKEUP (1 + 37)
#define IRQ_DOVE_SDIO1_WAKEUP (1 + 38)
#define IRQ_DOVE_XOR_00 (1 + 39)
#define IRQ_DOVE_XOR_01 (1 + 40)
#define IRQ_DOVE_XOR0_ERR (1 + 41)
#define IRQ_DOVE_XOR_10 (1 + 42)
#define IRQ_DOVE_XOR_11 (1 + 43)
#define IRQ_DOVE_XOR1_ERR (1 + 44)
#define IRQ_DOVE_LCD_DCON (1 + 45)
#define IRQ_DOVE_LCD1 (1 + 46)
#define IRQ_DOVE_LCD0 (1 + 47)
#define IRQ_DOVE_GPU (1 + 48)
#define IRQ_DOVE_PERFORM_MNTR (1 + 49)
#define IRQ_DOVE_VPRO_DMA1 (1 + 51)
#define IRQ_DOVE_SSP_TIMER (1 + 54)
#define IRQ_DOVE_SSP (1 + 55)
#define IRQ_DOVE_MC_L2_ERR (1 + 56)
#define IRQ_DOVE_CRYPTO_ERR (1 + 59)
#define IRQ_DOVE_GPIO_24_31 (1 + 60)
#define IRQ_DOVE_HIGH_GPIO (1 + 61)
#define IRQ_DOVE_SATA (1 + 62)
/*
* DOVE General Purpose Pins
*/
#define IRQ_DOVE_GPIO_START 64
#define IRQ_DOVE_GPIO_START 65
#define NR_GPIO_IRQS 64
/*

8
arch/arm/mach-dove/irq.c
View File

@ -126,14 +126,14 @@ __exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
if (stat) {
unsigned int hwirq = __fls(stat);
unsigned int hwirq = 1 + __fls(stat);
handle_IRQ(hwirq, regs);
return;
}
stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
if (stat) {
unsigned int hwirq = 32 + __fls(stat);
unsigned int hwirq = 33 + __fls(stat);
handle_IRQ(hwirq, regs);
return;
}
@ -144,8 +144,8 @@ void __init dove_init_irq(void)
{
int i;
orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
#ifdef CONFIG_MULTI_IRQ_HANDLER
set_handle_irq(dove_legacy_handle_irq);

3
arch/arm/mach-mvebu/pm-board.c
View File

@ -43,6 +43,9 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
ackcmd |= BIT(pic_raw_gpios[i]);
srcmd = cpu_to_le32(srcmd);
ackcmd = cpu_to_le32(ackcmd);
/*
* Wait a while, the PIC needs quite a bit of time between the
* two GPIO commands.

13
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -717,6 +717,19 @@
phy-names = "sata-phy";
};
sbgpio: sbgpio@17001000{
compatible = "apm,xgene-gpio-sb";
reg = <0x0 0x17001000 0x0 0x400>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <0x0 0x28 0x1>,
<0x0 0x29 0x1>,
<0x0 0x2a 0x1>,
<0x0 0x2b 0x1>,
<0x0 0x2c 0x1>,
<0x0 0x2d 0x1>;
};
rtc: rtc@10510000 {
compatible = "apm,xgene-rtc";
reg = <0x0 0x10510000 0x0 0x400>;

49
drivers/mmc/host/omap_hsmmc.c
View File

@ -43,6 +43,7 @@
#include <linux/regulator/consumer.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/pm_wakeirq.h>
#include <linux/platform_data/hsmmc-omap.h>
/* OMAP HSMMC Host Controller Registers */
@ -218,7 +219,6 @@ struct omap_hsmmc_host {
unsigned int flags;
#define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
#define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
#define HSMMC_WAKE_IRQ_ENABLED (1 << 2)
struct omap_hsmmc_next next_data;
struct omap_hsmmc_platform_data *pdata;
@ -1117,22 +1117,6 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
{
struct omap_hsmmc_host *host = dev_id;
/* cirq is level triggered, disable to avoid infinite loop */
spin_lock(&host->irq_lock);
if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
disable_irq_nosync(host->wake_irq);
host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
}
spin_unlock(&host->irq_lock);
pm_request_resume(host->dev); /* no use counter */
return IRQ_HANDLED;
}
static void set_sd_bus_power(struct omap_hsmmc_host *host)
{
unsigned long i;
@ -1665,7 +1649,6 @@ static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
{
struct mmc_host *mmc = host->mmc;
int ret;
/*
@ -1677,11 +1660,7 @@ static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
if (!host->dev->of_node || !host->wake_irq)
return -ENODEV;
/* Prevent auto-enabling of IRQ */
irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
mmc_hostname(mmc), host);
ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
if (ret) {
dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
goto err;
@ -1718,7 +1697,7 @@ static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
return 0;
err_free_irq:
devm_free_irq(host->dev, host->wake_irq, host);
dev_pm_clear_wake_irq(host->dev);
err:
dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
host->wake_irq = 0;
@ -2007,6 +1986,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
}
device_init_wakeup(&pdev->dev, true);
pm_runtime_enable(host->dev);
pm_runtime_get_sync(host->dev);
pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
@ -2147,6 +2127,7 @@ err_slot_name:
if (host->use_reg)
omap_hsmmc_reg_put(host);
err_irq:
device_init_wakeup(&pdev->dev, false);
if (host->tx_chan)
dma_release_channel(host->tx_chan);
if (host->rx_chan)
@ -2178,6 +2159,7 @@ static int omap_hsmmc_remove(struct platform_device *pdev)
pm_runtime_put_sync(host->dev);
pm_runtime_disable(host->dev);
device_init_wakeup(&pdev->dev, false);
if (host->dbclk)
clk_disable_unprepare(host->dbclk);
@ -2204,11 +2186,6 @@ static int omap_hsmmc_suspend(struct device *dev)
OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
}
/* do not wake up due to sdio irq */
if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
!(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
disable_irq(host->wake_irq);
if (host->dbclk)
clk_disable_unprepare(host->dbclk);
@ -2233,11 +2210,6 @@ static int omap_hsmmc_resume(struct device *dev)
omap_hsmmc_conf_bus_power(host);
omap_hsmmc_protect_card(host);
if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
!(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
enable_irq(host->wake_irq);
pm_runtime_mark_last_busy(host->dev);
pm_runtime_put_autosuspend(host->dev);
return 0;
@ -2277,10 +2249,6 @@ static int omap_hsmmc_runtime_suspend(struct device *dev)
}
pinctrl_pm_select_idle_state(dev);
WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
enable_irq(host->wake_irq);
host->flags |= HSMMC_WAKE_IRQ_ENABLED;
} else {
pinctrl_pm_select_idle_state(dev);
}
@ -2302,11 +2270,6 @@ static int omap_hsmmc_runtime_resume(struct device *dev)
spin_lock_irqsave(&host->irq_lock, flags);
if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
(host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
/* sdio irq flag can't change while in runtime suspend */
if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
disable_irq_nosync(host->wake_irq);
host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
}
pinctrl_pm_select_default_state(host->dev);

2
drivers/soc/qcom/spm.c
View File

@ -260,7 +260,7 @@ static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
/* We have atleast one power down mode */
cpumask_clear(&mask);
cpumask_set_cpu(cpu, &mask);
qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
qcom_scm_set_warm_boot_addr(cpu_resume_arm, &mask);
}
per_cpu(qcom_idle_ops, cpu) = fns;

58
drivers/tty/serial/8250/8250_omap.c
View File

@ -22,6 +22,7 @@
#include <linux/pm_runtime.h>
#include <linux/console.h>
#include <linux/pm_qos.h>
#include <linux/pm_wakeirq.h>
#include <linux/dma-mapping.h>
#include "8250.h"
@ -552,17 +553,6 @@ static void omap8250_uart_qos_work(struct work_struct *work)
pm_qos_update_request(&priv->pm_qos_request, priv->latency);
}
static irqreturn_t omap_wake_irq(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
int ret;
ret = port->handle_irq(port);
if (ret)
return IRQ_HANDLED;
return IRQ_NONE;
}
#ifdef CONFIG_SERIAL_8250_DMA
static int omap_8250_dma_handle_irq(struct uart_port *port);
#endif
@ -596,11 +586,9 @@ static int omap_8250_startup(struct uart_port *port)
int ret;
if (priv->wakeirq) {
ret = request_irq(priv->wakeirq, omap_wake_irq,
port->irqflags, "uart wakeup irq", port);
ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
if (ret)
return ret;
disable_irq(priv->wakeirq);
}
pm_runtime_get_sync(port->dev);
@ -649,8 +637,7 @@ static int omap_8250_startup(struct uart_port *port)
err:
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
if (priv->wakeirq)
free_irq(priv->wakeirq, port);
dev_pm_clear_wake_irq(port->dev);
return ret;
}
@ -682,10 +669,8 @@ static void omap_8250_shutdown(struct uart_port *port)
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
free_irq(port->irq, port);
if (priv->wakeirq)
free_irq(priv->wakeirq, port);
dev_pm_clear_wake_irq(port->dev);
}
static void omap_8250_throttle(struct uart_port *port)
@ -1226,31 +1211,6 @@ static int omap8250_remove(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_PM
static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv,
bool enable)
{
if (!priv->wakeirq)
return;
if (enable)
enable_irq(priv->wakeirq);
else
disable_irq_nosync(priv->wakeirq);
}
static void omap8250_enable_wakeup(struct omap8250_priv *priv,
bool enable)
{
if (enable == priv->wakeups_enabled)
return;
omap8250_enable_wakeirq(priv, enable);
priv->wakeups_enabled = enable;
}
#endif
#ifdef CONFIG_PM_SLEEP
static int omap8250_prepare(struct device *dev)
{
@ -1277,11 +1237,6 @@ static int omap8250_suspend(struct device *dev)
serial8250_suspend_port(priv->line);
flush_work(&priv->qos_work);
if (device_may_wakeup(dev))
omap8250_enable_wakeup(priv, true);
else
omap8250_enable_wakeup(priv, false);
return 0;
}
@ -1289,9 +1244,6 @@ static int omap8250_resume(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
omap8250_enable_wakeup(priv, false);
serial8250_resume_port(priv->line);
return 0;
}
@ -1333,7 +1285,6 @@ static int omap8250_runtime_suspend(struct device *dev)
return -EBUSY;
}
omap8250_enable_wakeup(priv, true);
if (up->dma)
omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT);
@ -1354,7 +1305,6 @@ static int omap8250_runtime_resume(struct device *dev)
return 0;
up = serial8250_get_port(priv->line);
omap8250_enable_wakeup(priv, false);
loss_cntx = omap8250_lost_context(up);
if (loss_cntx)

35
drivers/tty/serial/omap-serial.c
View File

@ -38,6 +38,7 @@
#include <linux/serial_core.h>
#include <linux/irq.h>
#include <linux/pm_runtime.h>
#include <linux/pm_wakeirq.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/gpio.h>
@ -160,7 +161,6 @@ struct uart_omap_port {
unsigned long port_activity;
int context_loss_cnt;
u32 errata;
u8 wakeups_enabled;
u32 features;
int rts_gpio;
@ -209,28 +209,11 @@ static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
return pdata->get_context_loss_count(up->dev);
}
static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
bool enable)
{
if (!up->wakeirq)
return;
if (enable)
enable_irq(up->wakeirq);
else
disable_irq_nosync(up->wakeirq);
}
/* REVISIT: Remove this when omap3 boots in device tree only mode */
static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
{
struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
if (enable == up->wakeups_enabled)
return;
serial_omap_enable_wakeirq(up, enable);
up->wakeups_enabled = enable;
if (!pdata || !pdata->enable_wakeup)
return;
@ -750,13 +733,11 @@ static int serial_omap_startup(struct uart_port *port)
/* Optional wake-up IRQ */
if (up->wakeirq) {
retval = request_irq(up->wakeirq, serial_omap_irq,
up->port.irqflags, up->name, up);
retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
if (retval) {
free_irq(up->port.irq, up);
return retval;
}
disable_irq(up->wakeirq);
}
dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
@ -845,8 +826,7 @@ static void serial_omap_shutdown(struct uart_port *port)
pm_runtime_mark_last_busy(up->dev);
pm_runtime_put_autosuspend(up->dev);
free_irq(up->port.irq, up);
if (up->wakeirq)
free_irq(up->wakeirq, up);
dev_pm_clear_wake_irq(up->dev);
}
static void serial_omap_uart_qos_work(struct work_struct *work)
@ -1139,13 +1119,6 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
serial_out(up, UART_EFR, efr);
serial_out(up, UART_LCR, 0);
if (!device_may_wakeup(up->dev)) {
if (!state)
pm_runtime_forbid(up->dev);
else
pm_runtime_allow(up->dev);
}
pm_runtime_mark_last_busy(up->dev);
pm_runtime_put_autosuspend(up->dev);
}