gpio-pch: modify gpio_nums and mask
Currently, the number of GPIO pins is set fixed value(=12). Also PIN MASK is set as '0xfff'. However the pins differs by IOH. This patch sets the value correctly. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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c3520a1a84
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d4260e6ddd
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@ -18,9 +18,6 @@
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#include <linux/pci.h>
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#include <linux/gpio.h>
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#define PCH_GPIO_ALL_PINS 0xfff /* Mask for GPIO pins 0 to 11 */
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#define GPIO_NUM_PINS 12 /* Specifies number of GPIO PINS GPIO0-GPIO11 */
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struct pch_regs {
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u32 ien;
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u32 istatus;
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@ -37,6 +34,19 @@ struct pch_regs {
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u32 reset;
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};
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enum pch_type_t {
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INTEL_EG20T_PCH,
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OKISEMI_ML7223m_IOH, /* OKISEMI ML7223 IOH PCIe Bus-m */
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OKISEMI_ML7223n_IOH /* OKISEMI ML7223 IOH PCIe Bus-n */
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};
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/* Specifies number of GPIO PINS */
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static int gpio_pins[] = {
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[INTEL_EG20T_PCH] = 12,
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[OKISEMI_ML7223m_IOH] = 8,
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[OKISEMI_ML7223n_IOH] = 8,
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};
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/**
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* struct pch_gpio_reg_data - The register store data.
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* @po_reg: To store contents of PO register.
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@ -55,6 +65,7 @@ struct pch_gpio_reg_data {
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* @gpio: Data for GPIO infrastructure.
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* @pch_gpio_reg: Memory mapped Register data is saved here
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* when suspend.
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* @ioh: IOH ID
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* @spinlock: Used for register access protection in
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* interrupt context pch_irq_mask,
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* pch_irq_unmask and pch_irq_type;
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@ -66,6 +77,7 @@ struct pch_gpio {
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struct gpio_chip gpio;
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struct pch_gpio_reg_data pch_gpio_reg;
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struct mutex lock;
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enum pch_type_t ioh;
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spinlock_t spinlock;
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};
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@ -100,7 +112,7 @@ static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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u32 reg_val;
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mutex_lock(&chip->lock);
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pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS;
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pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
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pm |= (1 << nr);
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iowrite32(pm, &chip->reg->pm);
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@ -122,7 +134,7 @@ static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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u32 pm;
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mutex_lock(&chip->lock);
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pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; /*bits 0-11*/
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pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
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pm &= ~(1 << nr);
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iowrite32(pm, &chip->reg->pm);
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mutex_unlock(&chip->lock);
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@ -162,7 +174,7 @@ static void pch_gpio_setup(struct pch_gpio *chip)
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gpio->set = pch_gpio_set;
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gpio->dbg_show = NULL;
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gpio->base = -1;
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gpio->ngpio = GPIO_NUM_PINS;
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gpio->ngpio = gpio_pins[chip->ioh];
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gpio->can_sleep = 0;
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}
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@ -196,6 +208,13 @@ static int __devinit pch_gpio_probe(struct pci_dev *pdev,
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goto err_iomap;
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}
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if (pdev->device == 0x8803)
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chip->ioh = INTEL_EG20T_PCH;
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else if (pdev->device == 0x8014)
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chip->ioh = OKISEMI_ML7223m_IOH;
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else if (pdev->device == 0x8043)
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chip->ioh = OKISEMI_ML7223n_IOH;
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chip->reg = chip->base;
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pci_set_drvdata(pdev, chip);
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mutex_init(&chip->lock);
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