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Clk: SPEAr1340: Update sys clock parent array 

sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl
register bit no. 23:25, with following possibilities

   0XX: pll1_clk
   10X: sys_synth_clk
   110: pll2_clk
   111: pll3_clk

Out of several possibilities (h/w wise) to select same clock parent for
sys_clk, current clock implementation was considering just one value.

When bootloader programmed different (valid) value to select a clock
parent then Linux breaks.

Here, we try to include all possibilities which can lead to same
clock selection thus making Linux independent of bootloader selection
values.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
wifi-calibration
Vipul Kumar Samar 2012-07-06 15:52:36 +05:30 committed by Shiraz Hashim
parent d9ba8db215
commit d4f513ff12
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/spear/spear1340_clock.c
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@ -369,8 +369,8 @@ static struct frac_rate_tbl gen_rtbl[] = {
/* clock parents */
static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
"sys_syn_clk", "none", "pll2_clk", "pll3_clk", };
static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
"pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", };
static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",