sata highbank: add bit-banged SGPIO driver support
Highbank supports SGPIO by bit-banging out the SGPIO signals over three GPIO pins defined in the DTB. Add support for this SGPIO functionality. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Mark Langsdorf
Tejun Heo
parent
439d7a358f
commit
d50b110f14
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@ -12,6 +12,11 @@ Optional properties:
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- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
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SATA port to a combophy and a lane within that
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combophy
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- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
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which indicates that the driver supports SGPIO
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indicator lights using the indicated GPIOs
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- calxeda,led-order : a u32 array that map port numbers to offsets within the
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SGPIO bitstream.
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- dma-coherent : Present if dma operations are coherent
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Example:
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@ -33,6 +33,8 @@
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calxeda,port-phys = <&combophy5 0 &combophy0 0
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&combophy0 1 &combophy0 2
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&combophy0 3>;
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calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
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calxeda,led-order = <4 0 1 2 3>;
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};
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sdhci@ffe0e000 {
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@ -322,6 +322,7 @@ struct ahci_host_priv {
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u32 em_buf_sz; /* EM buffer size in byte */
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u32 em_msg_type; /* EM message type */
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struct clk *clk; /* Only for platforms supporting clk */
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void *plat_data; /* Other platform data */
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};
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extern int ahci_ignore_sss;
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@ -33,6 +33,9 @@
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include "ahci.h"
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#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
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@ -66,6 +69,146 @@ struct phy_lane_info {
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};
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static struct phy_lane_info port_data[CPHY_PORT_COUNT];
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static DEFINE_SPINLOCK(sgpio_lock);
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#define SCLOCK 0
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#define SLOAD 1
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#define SDATA 2
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#define SGPIO_PINS 3
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#define SGPIO_PORTS 8
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/* can be cast as an ahci_host_priv for compatibility with most functions */
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struct ecx_plat_data {
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u32 n_ports;
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unsigned sgpio_gpio[SGPIO_PINS];
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u32 sgpio_pattern;
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u32 port_to_sgpio[SGPIO_PORTS];
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};
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#define SGPIO_SIGNALS 3
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#define ECX_ACTIVITY_BITS 0x300000
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#define ECX_ACTIVITY_SHIFT 2
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#define ECX_LOCATE_BITS 0x80000
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#define ECX_LOCATE_SHIFT 1
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#define ECX_FAULT_BITS 0x400000
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#define ECX_FAULT_SHIFT 0
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static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
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u32 shift)
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{
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return 1 << (3 * pdata->port_to_sgpio[port] + shift);
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}
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static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
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{
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if (state & ECX_ACTIVITY_BITS)
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pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
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ECX_ACTIVITY_SHIFT);
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else
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pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
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ECX_ACTIVITY_SHIFT);
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if (state & ECX_LOCATE_BITS)
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pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
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ECX_LOCATE_SHIFT);
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else
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pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
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ECX_LOCATE_SHIFT);
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if (state & ECX_FAULT_BITS)
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pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
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ECX_FAULT_SHIFT);
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else
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pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
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ECX_FAULT_SHIFT);
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}
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/*
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* Tell the LED controller that the signal has changed by raising the clock
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* line for 50 uS and then lowering it for 50 uS.
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*/
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static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
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{
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gpio_set_value(pdata->sgpio_gpio[SCLOCK], 1);
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udelay(50);
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gpio_set_value(pdata->sgpio_gpio[SCLOCK], 0);
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udelay(50);
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}
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static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
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ssize_t size)
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{
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struct ahci_host_priv *hpriv = ap->host->private_data;
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struct ecx_plat_data *pdata = (struct ecx_plat_data *) hpriv->plat_data;
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struct ahci_port_priv *pp = ap->private_data;
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unsigned long flags;
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int pmp, i;
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struct ahci_em_priv *emp;
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u32 sgpio_out;
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/* get the slot number from the message */
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pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
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if (pmp < EM_MAX_SLOTS)
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emp = &pp->em_priv[pmp];
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else
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return -EINVAL;
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if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
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return size;
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spin_lock_irqsave(&sgpio_lock, flags);
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ecx_parse_sgpio(pdata, ap->port_no, state);
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sgpio_out = pdata->sgpio_pattern;
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gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
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ecx_led_cycle_clock(pdata);
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gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
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/*
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* bit-bang out the SGPIO pattern, by consuming a bit and then
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* clocking it out.
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*/
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for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
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gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
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sgpio_out >>= 1;
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ecx_led_cycle_clock(pdata);
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}
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/* save off new led state for port/slot */
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emp->led_state = state;
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spin_unlock_irqrestore(&sgpio_lock, flags);
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return size;
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}
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static void highbank_set_em_messages(struct device *dev,
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struct ahci_host_priv *hpriv,
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struct ata_port_info *pi)
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{
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struct device_node *np = dev->of_node;
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struct ecx_plat_data *pdata = hpriv->plat_data;
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int i;
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int err;
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for (i = 0; i < SGPIO_PINS; i++) {
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err = of_get_named_gpio(np, "calxeda,sgpio-gpio", i);
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if (IS_ERR_VALUE(err))
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return;
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pdata->sgpio_gpio[i] = err;
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err = gpio_request(pdata->sgpio_gpio[i], "CX SGPIO");
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if (err) {
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pr_err("sata_highbank gpio_request %d failed: %d\n",
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i, err);
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return;
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}
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gpio_direction_output(pdata->sgpio_gpio[i], 1);
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}
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of_property_read_u32_array(np, "calxeda,led-order",
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pdata->port_to_sgpio,
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pdata->n_ports);
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/* store em_loc */
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hpriv->em_loc = 0;
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hpriv->em_buf_sz = 4;
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hpriv->em_msg_type = EM_MSG_TYPE_LED;
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pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY;
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}
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static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
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{
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u32 data;
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@ -241,6 +384,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
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static struct ata_port_operations ahci_highbank_ops = {
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.inherits = &ahci_ops,
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.hardreset = ahci_highbank_hardreset,
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.transmit_led_message = ecx_transmit_led_message,
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};
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static const struct ata_port_info ahci_highbank_port_info = {
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@ -264,12 +408,13 @@ static int ahci_highbank_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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struct ecx_plat_data *pdata;
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struct ata_host *host;
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struct resource *mem;
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int irq;
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int n_ports;
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int i;
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int rc;
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u32 n_ports;
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struct ata_port_info pi = ahci_highbank_port_info;
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const struct ata_port_info *ppi[] = { &pi, NULL };
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@ -290,6 +435,11 @@ static int ahci_highbank_probe(struct platform_device *pdev)
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dev_err(dev, "can't alloc ahci_host_priv\n");
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return -ENOMEM;
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}
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pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata) {
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dev_err(dev, "can't alloc ecx_plat_data\n");
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return -ENOMEM;
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}
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hpriv->flags |= (unsigned long)pi.private_data;
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@ -313,8 +463,6 @@ static int ahci_highbank_probe(struct platform_device *pdev)
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if (hpriv->cap & HOST_CAP_PMP)
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pi.flags |= ATA_FLAG_PMP;
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ahci_set_em_messages(hpriv, &pi);
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/* CAP.NP sometimes indicate the index of the last enabled
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* port, at other times, that of the last possible port, so
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* determining the maximum port number requires looking at
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@ -322,6 +470,10 @@ static int ahci_highbank_probe(struct platform_device *pdev)
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*/
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n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
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pdata->n_ports = n_ports;
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hpriv->plat_data = pdata;
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highbank_set_em_messages(dev, hpriv, &pi);
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host = ata_host_alloc_pinfo(dev, ppi, n_ports);
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if (!host) {
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rc = -ENOMEM;
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@ -333,9 +485,6 @@ static int ahci_highbank_probe(struct platform_device *pdev)
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if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
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host->flags |= ATA_HOST_PARALLEL_SCAN;
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if (pi.flags & ATA_FLAG_EM)
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ahci_reset_em(host);
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for (i = 0; i < host->n_ports; i++) {
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struct ata_port *ap = host->ports[i];
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