clk: tegra: override bits for Tegra114 PLLM
Define override bits for Tegra114 PLLM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up trivial merge conflict]
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@ -251,6 +251,10 @@
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#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
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#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
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#define CLK_SOURCE_EMC 0x19c
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#define CLK_SOURCE_EMC 0x19c
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/* PLLM override registers */
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#define PMC_PLLM_WB0_OVERRIDE 0x1dc
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#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
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static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
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static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
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static void __iomem *clk_base;
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static void __iomem *clk_base;
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@ -395,10 +399,13 @@ static struct tegra_clk_pll_params pll_c3_params = {
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static struct div_nmp pllm_nmp = {
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static struct div_nmp pllm_nmp = {
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.divm_shift = 0,
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.divm_shift = 0,
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.divm_width = 8,
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.divm_width = 8,
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.override_divm_shift = 0,
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.divn_shift = 8,
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.divn_shift = 8,
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.divn_width = 8,
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.divn_width = 8,
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.override_divn_shift = 8,
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.divp_shift = 20,
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.divp_shift = 20,
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.divp_width = 1,
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.divp_width = 1,
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.override_divp_shift = 27,
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};
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};
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static struct pdiv_map pllm_p[] = {
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static struct pdiv_map pllm_p[] = {
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@ -431,6 +438,8 @@ static struct tegra_clk_pll_params pll_m_params = {
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.max_p = 2,
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.max_p = 2,
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.pdiv_tohw = pllm_p,
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.pdiv_tohw = pllm_p,
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.div_nmp = &pllm_nmp,
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.div_nmp = &pllm_nmp,
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.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
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.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
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};
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};
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static struct div_nmp pllp_nmp = {
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static struct div_nmp pllp_nmp = {
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