clk: divider: add CLK_DIVIDER_HIWORD_MASK flag
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -227,8 +227,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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val = readl(divider->reg);
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val &= ~(div_mask(divider) << divider->shift);
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = div_mask(divider) << (divider->shift + 16);
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} else {
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val = readl(divider->reg);
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val &= ~(div_mask(divider) << divider->shift);
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}
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val |= value << divider->shift;
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writel(val, divider->reg);
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@ -255,6 +259,13 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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struct clk *clk;
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struct clk_init_data init;
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if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
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if (width + shift > 16) {
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pr_warn("divider value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the divider */
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div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
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if (!div) {
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@ -257,6 +257,10 @@ struct clk_div_table {
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* Some hardware implementations gracefully handle this case and allow a
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* zero divisor by not modifying their input clock
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* (divide by one / bypass).
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* CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
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* of this register, and mask of divider bits are in higher 16-bit of this
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* register. While setting the divider bits, higher 16-bit should also be
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* updated to indicate changing divider bits.
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*/
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struct clk_divider {
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struct clk_hw hw;
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@ -271,6 +275,7 @@ struct clk_divider {
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#define CLK_DIVIDER_ONE_BASED BIT(0)
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
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#define CLK_DIVIDER_HIWORD_MASK BIT(3)
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extern const struct clk_ops clk_divider_ops;
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struct clk *clk_register_divider(struct device *dev, const char *name,
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