Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI/cardbus: Add a fixup hook and fix powerpc PCI: change PCI nomenclature in drivers/pci/ (non-comment changes) PCI: change PCI nomenclature in drivers/pci/ (comment changes) PCI: fix section mismatch on update_res() PCI: add Intel 82599 Virtual Function specific reset method PCI: add Intel USB specific reset method PCI: support device-specific reset methods PCI: Handle case when no pci device can provide cache line size hint PCI/PM: Propagate wake-up enable for PCIe devices too vgaarbiter: fix a typo in the vgaarbiter Documentation
This commit is contained in:
commit
d661d76b02
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@ -103,7 +103,7 @@ I.2 libpciaccess
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||||||
----------------
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----------------
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||||||
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To use the vga arbiter char device it was implemented an API inside the
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To use the vga arbiter char device it was implemented an API inside the
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libpciaccess library. One fieldd was added to struct pci_device (each device
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libpciaccess library. One field was added to struct pci_device (each device
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on the system):
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on the system):
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/* the type of resource decoded by the device */
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/* the type of resource decoded by the device */
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@ -1107,6 +1107,12 @@ void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
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list_for_each_entry(dev, &bus->devices, bus_list) {
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list_for_each_entry(dev, &bus->devices, bus_list) {
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struct dev_archdata *sd = &dev->dev.archdata;
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struct dev_archdata *sd = &dev->dev.archdata;
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/* Cardbus can call us to add new devices to a bus, so ignore
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* those who are already fully discovered
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*/
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if (dev->is_added)
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continue;
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/* Setup OF node pointer in archdata */
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/* Setup OF node pointer in archdata */
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sd->of_node = pci_device_to_OF_node(dev);
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sd->of_node = pci_device_to_OF_node(dev);
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@ -1147,6 +1153,13 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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}
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}
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EXPORT_SYMBOL(pcibios_fixup_bus);
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EXPORT_SYMBOL(pcibios_fixup_bus);
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void __devinit pci_fixup_cardbus(struct pci_bus *bus)
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{
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/* Now fixup devices on that bus */
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pcibios_setup_bus_devices(bus);
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}
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static int skip_isa_ioresource_align(struct pci_dev *dev)
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static int skip_isa_ioresource_align(struct pci_dev *dev)
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{
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{
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if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
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if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
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@ -51,7 +51,7 @@ void x86_pci_root_bus_res_quirks(struct pci_bus *b)
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}
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}
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}
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}
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void __init update_res(struct pci_root_info *info, size_t start,
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void __devinit update_res(struct pci_root_info *info, size_t start,
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size_t end, unsigned long flags, int merge)
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size_t end, unsigned long flags, int merge)
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{
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{
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int i;
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int i;
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@ -121,7 +121,7 @@ struct controller {
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#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
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#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
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#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
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#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
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/* AMD PCIX bridge registers */
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/* AMD PCI-X bridge registers */
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#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
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#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
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#define PCIX_MISCII_OFFSET 0x48
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#define PCIX_MISCII_OFFSET 0x48
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#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
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#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
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@ -305,7 +305,7 @@ struct device_domain_info {
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int segment; /* PCI domain */
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int segment; /* PCI domain */
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u8 bus; /* PCI bus number */
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u8 bus; /* PCI bus number */
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u8 devfn; /* PCI devfn number */
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u8 devfn; /* PCI devfn number */
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struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
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struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
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struct intel_iommu *iommu; /* IOMMU used by this device */
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struct intel_iommu *iommu; /* IOMMU used by this device */
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struct dmar_domain *domain; /* pointer to domain */
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struct dmar_domain *domain; /* pointer to domain */
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};
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};
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@ -1604,7 +1604,7 @@ domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
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return ret;
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return ret;
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parent = parent->bus->self;
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parent = parent->bus->self;
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}
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}
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if (pci_is_pcie(tmp)) /* this is a PCIE-to-PCI bridge */
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if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
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return domain_context_mapping_one(domain,
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return domain_context_mapping_one(domain,
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pci_domain_nr(tmp->subordinate),
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pci_domain_nr(tmp->subordinate),
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tmp->subordinate->number, 0,
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tmp->subordinate->number, 0,
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@ -3325,7 +3325,7 @@ static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
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parent->devfn);
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parent->devfn);
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parent = parent->bus->self;
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parent = parent->bus->self;
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}
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}
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if (pci_is_pcie(tmp)) /* this is a PCIE-to-PCI bridge */
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if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
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iommu_detach_dev(iommu,
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iommu_detach_dev(iommu,
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tmp->subordinate->number, 0);
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tmp->subordinate->number, 0);
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else /* this is a legacy PCI bridge */
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else /* this is a legacy PCI bridge */
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|
|
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@ -528,7 +528,7 @@ int set_msi_sid(struct irte *irte, struct pci_dev *dev)
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|
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bridge = pci_find_upstream_pcie_bridge(dev);
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bridge = pci_find_upstream_pcie_bridge(dev);
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if (bridge) {
|
if (bridge) {
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if (pci_is_pcie(bridge))/* this is a PCIE-to-PCI/PCIX bridge */
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if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
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set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
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set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
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(bridge->bus->number << 8) | dev->bus->number);
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(bridge->bus->number << 8) | dev->bus->number);
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else /* this is a legacy PCI bridge */
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else /* this is a legacy PCI bridge */
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||||||
|
|
|
@ -112,11 +112,7 @@ static bool acpi_pci_can_wakeup(struct pci_dev *dev)
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static void acpi_pci_propagate_wakeup_enable(struct pci_bus *bus, bool enable)
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static void acpi_pci_propagate_wakeup_enable(struct pci_bus *bus, bool enable)
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||||||
{
|
{
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||||||
while (bus->parent) {
|
while (bus->parent) {
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||||||
struct pci_dev *bridge = bus->self;
|
if (!acpi_pm_device_sleep_wake(&bus->self->dev, enable))
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int ret;
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||||||
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ret = acpi_pm_device_sleep_wake(&bridge->dev, enable);
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||||||
if (!ret || pci_is_pcie(bridge))
|
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||||||
return;
|
return;
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bus = bus->parent;
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bus = bus->parent;
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}
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}
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@ -131,9 +127,7 @@ static int acpi_pci_sleep_wake(struct pci_dev *dev, bool enable)
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if (acpi_pci_can_wakeup(dev))
|
if (acpi_pci_can_wakeup(dev))
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return acpi_pm_device_sleep_wake(&dev->dev, enable);
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return acpi_pm_device_sleep_wake(&dev->dev, enable);
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||||||
if (!pci_is_pcie(dev))
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||||||
acpi_pci_propagate_wakeup_enable(dev->bus, enable);
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acpi_pci_propagate_wakeup_enable(dev->bus, enable);
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return 0;
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return 0;
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}
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}
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||||||
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|
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@ -1153,11 +1153,11 @@ pci_disable_device(struct pci_dev *dev)
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/**
|
/**
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* pcibios_set_pcie_reset_state - set reset state for device dev
|
* pcibios_set_pcie_reset_state - set reset state for device dev
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||||||
* @dev: the PCI-E device reset
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* @dev: the PCIe device reset
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* @state: Reset state to enter into
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* @state: Reset state to enter into
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*
|
*
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||||||
*
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*
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||||||
* Sets the PCI-E reset state for the device. This is the default
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* Sets the PCIe reset state for the device. This is the default
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* implementation. Architecture implementations can override this.
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* implementation. Architecture implementations can override this.
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*/
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*/
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int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
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int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
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||||||
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@ -1168,7 +1168,7 @@ int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
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|
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||||||
/**
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/**
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* pci_set_pcie_reset_state - set reset state for device dev
|
* pci_set_pcie_reset_state - set reset state for device dev
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* @dev: the PCI-E device reset
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* @dev: the PCIe device reset
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* @state: Reset state to enter into
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* @state: Reset state to enter into
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*
|
*
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||||||
*
|
*
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||||||
|
@ -2284,6 +2284,21 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
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return 0;
|
return 0;
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}
|
}
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|
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||||||
|
static int pci_dev_specific_reset(struct pci_dev *dev, int probe)
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|
{
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|
struct pci_dev_reset_methods *i;
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|
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||||||
|
for (i = pci_dev_reset_methods; i->reset; i++) {
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|
if ((i->vendor == dev->vendor ||
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|
i->vendor == (u16)PCI_ANY_ID) &&
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||||||
|
(i->device == dev->device ||
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|
i->device == (u16)PCI_ANY_ID))
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|
return i->reset(dev, probe);
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|
}
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|
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||||||
|
return -ENOTTY;
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}
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|
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||||||
static int pci_dev_reset(struct pci_dev *dev, int probe)
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static int pci_dev_reset(struct pci_dev *dev, int probe)
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{
|
{
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int rc;
|
int rc;
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||||||
|
@ -2296,6 +2311,10 @@ static int pci_dev_reset(struct pci_dev *dev, int probe)
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down(&dev->dev.sem);
|
down(&dev->dev.sem);
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}
|
}
|
||||||
|
|
||||||
|
rc = pci_dev_specific_reset(dev, probe);
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|
if (rc != -ENOTTY)
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||||||
|
goto done;
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||||||
|
|
||||||
rc = pcie_flr(dev, probe);
|
rc = pcie_flr(dev, probe);
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||||||
if (rc != -ENOTTY)
|
if (rc != -ENOTTY)
|
||||||
goto done;
|
goto done;
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||||||
|
@ -2779,6 +2798,11 @@ int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
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||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void __weak pci_fixup_cardbus(struct pci_bus *bus)
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||||||
|
{
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(pci_fixup_cardbus);
|
||||||
|
|
||||||
static int __init pci_setup(char *str)
|
static int __init pci_setup(char *str)
|
||||||
{
|
{
|
||||||
while (str) {
|
while (str) {
|
||||||
|
|
|
@ -313,4 +313,12 @@ static inline int pci_resource_alignment(struct pci_dev *dev,
|
||||||
|
|
||||||
extern void pci_enable_acs(struct pci_dev *dev);
|
extern void pci_enable_acs(struct pci_dev *dev);
|
||||||
|
|
||||||
|
struct pci_dev_reset_methods {
|
||||||
|
u16 vendor;
|
||||||
|
u16 device;
|
||||||
|
int (*reset)(struct pci_dev *dev, int probe);
|
||||||
|
};
|
||||||
|
|
||||||
|
extern struct pci_dev_reset_methods pci_dev_reset_methods[];
|
||||||
|
|
||||||
#endif /* DRIVERS_PCI_H */
|
#endif /* DRIVERS_PCI_H */
|
||||||
|
|
|
@ -3,14 +3,14 @@
|
||||||
#
|
#
|
||||||
|
|
||||||
config PCIEAER_INJECT
|
config PCIEAER_INJECT
|
||||||
tristate "PCIE AER error injector support"
|
tristate "PCIe AER error injector support"
|
||||||
depends on PCIEAER
|
depends on PCIEAER
|
||||||
default n
|
default n
|
||||||
help
|
help
|
||||||
This enables PCI Express Root Port Advanced Error Reporting
|
This enables PCI Express Root Port Advanced Error Reporting
|
||||||
(AER) software error injector.
|
(AER) software error injector.
|
||||||
|
|
||||||
Debuging PCIE AER code is quite difficult because it is hard
|
Debugging PCIe AER code is quite difficult because it is hard
|
||||||
to trigger various real hardware errors. Software based
|
to trigger various real hardware errors. Software based
|
||||||
error injection can fake almost all kinds of errors with the
|
error injection can fake almost all kinds of errors with the
|
||||||
help of a user space helper tool aer-inject, which can be
|
help of a user space helper tool aer-inject, which can be
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* PCIE AER software error injection support.
|
* PCIe AER software error injection support.
|
||||||
*
|
*
|
||||||
* Debuging PCIE AER code is quite difficult because it is hard to
|
* Debuging PCIe AER code is quite difficult because it is hard to
|
||||||
* trigger various real hardware errors. Software based error
|
* trigger various real hardware errors. Software based error
|
||||||
* injection can fake almost all kinds of errors with the help of a
|
* injection can fake almost all kinds of errors with the help of a
|
||||||
* user space helper tool aer-inject, which can be gotten from:
|
* user space helper tool aer-inject, which can be gotten from:
|
||||||
|
@ -484,5 +484,5 @@ static void __exit aer_inject_exit(void)
|
||||||
module_init(aer_inject_init);
|
module_init(aer_inject_init);
|
||||||
module_exit(aer_inject_exit);
|
module_exit(aer_inject_exit);
|
||||||
|
|
||||||
MODULE_DESCRIPTION("PCIE AER software error injector");
|
MODULE_DESCRIPTION("PCIe AER software error injector");
|
||||||
MODULE_LICENSE("GPL");
|
MODULE_LICENSE("GPL");
|
||||||
|
|
|
@ -155,7 +155,7 @@ static struct aer_rpc *aer_alloc_rpc(struct pcie_device *dev)
|
||||||
mutex_init(&rpc->rpc_mutex);
|
mutex_init(&rpc->rpc_mutex);
|
||||||
init_waitqueue_head(&rpc->wait_release);
|
init_waitqueue_head(&rpc->wait_release);
|
||||||
|
|
||||||
/* Use PCIE bus function to store rpc into PCIE device */
|
/* Use PCIe bus function to store rpc into PCIe device */
|
||||||
set_service_data(dev, rpc);
|
set_service_data(dev, rpc);
|
||||||
|
|
||||||
return rpc;
|
return rpc;
|
||||||
|
|
|
@ -24,7 +24,7 @@
|
||||||
*
|
*
|
||||||
* @return: Zero on success. Nonzero otherwise.
|
* @return: Zero on success. Nonzero otherwise.
|
||||||
*
|
*
|
||||||
* Invoked when PCIE bus loads AER service driver. To avoid conflict with
|
* Invoked when PCIe bus loads AER service driver. To avoid conflict with
|
||||||
* BIOS AER support requires BIOS to yield AER control to OS native driver.
|
* BIOS AER support requires BIOS to yield AER control to OS native driver.
|
||||||
**/
|
**/
|
||||||
int aer_osc_setup(struct pcie_device *pciedev)
|
int aer_osc_setup(struct pcie_device *pciedev)
|
||||||
|
|
|
@ -587,7 +587,7 @@ static void handle_error_source(struct pcie_device *aerdev,
|
||||||
* aer_enable_rootport - enable Root Port's interrupts when receiving messages
|
* aer_enable_rootport - enable Root Port's interrupts when receiving messages
|
||||||
* @rpc: pointer to a Root Port data structure
|
* @rpc: pointer to a Root Port data structure
|
||||||
*
|
*
|
||||||
* Invoked when PCIE bus loads AER service driver.
|
* Invoked when PCIe bus loads AER service driver.
|
||||||
*/
|
*/
|
||||||
void aer_enable_rootport(struct aer_rpc *rpc)
|
void aer_enable_rootport(struct aer_rpc *rpc)
|
||||||
{
|
{
|
||||||
|
@ -597,7 +597,7 @@ void aer_enable_rootport(struct aer_rpc *rpc)
|
||||||
u32 reg32;
|
u32 reg32;
|
||||||
|
|
||||||
pos = pci_pcie_cap(pdev);
|
pos = pci_pcie_cap(pdev);
|
||||||
/* Clear PCIE Capability's Device Status */
|
/* Clear PCIe Capability's Device Status */
|
||||||
pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, ®16);
|
pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, ®16);
|
||||||
pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16);
|
pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16);
|
||||||
|
|
||||||
|
@ -631,7 +631,7 @@ void aer_enable_rootport(struct aer_rpc *rpc)
|
||||||
* disable_root_aer - disable Root Port's interrupts when receiving messages
|
* disable_root_aer - disable Root Port's interrupts when receiving messages
|
||||||
* @rpc: pointer to a Root Port data structure
|
* @rpc: pointer to a Root Port data structure
|
||||||
*
|
*
|
||||||
* Invoked when PCIE bus unloads AER service driver.
|
* Invoked when PCIe bus unloads AER service driver.
|
||||||
*/
|
*/
|
||||||
static void disable_root_aer(struct aer_rpc *rpc)
|
static void disable_root_aer(struct aer_rpc *rpc)
|
||||||
{
|
{
|
||||||
|
|
|
@ -184,7 +184,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
|
||||||
|
|
||||||
if (info->status == 0) {
|
if (info->status == 0) {
|
||||||
AER_PR(info, dev,
|
AER_PR(info, dev,
|
||||||
"PCIE Bus Error: severity=%s, type=Unaccessible, "
|
"PCIe Bus Error: severity=%s, type=Unaccessible, "
|
||||||
"id=%04x(Unregistered Agent ID)\n",
|
"id=%04x(Unregistered Agent ID)\n",
|
||||||
aer_error_severity_string[info->severity], id);
|
aer_error_severity_string[info->severity], id);
|
||||||
} else {
|
} else {
|
||||||
|
@ -194,7 +194,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
|
||||||
agent = AER_GET_AGENT(info->severity, info->status);
|
agent = AER_GET_AGENT(info->severity, info->status);
|
||||||
|
|
||||||
AER_PR(info, dev,
|
AER_PR(info, dev,
|
||||||
"PCIE Bus Error: severity=%s, type=%s, id=%04x(%s)\n",
|
"PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n",
|
||||||
aer_error_severity_string[info->severity],
|
aer_error_severity_string[info->severity],
|
||||||
aer_error_layer[layer], id, aer_agent_string[agent]);
|
aer_error_layer[layer], id, aer_agent_string[agent]);
|
||||||
|
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
/*
|
/*
|
||||||
* File: drivers/pci/pcie/aspm.c
|
* File: drivers/pci/pcie/aspm.c
|
||||||
* Enabling PCIE link L0s/L1 state and Clock Power Management
|
* Enabling PCIe link L0s/L1 state and Clock Power Management
|
||||||
*
|
*
|
||||||
* Copyright (C) 2007 Intel
|
* Copyright (C) 2007 Intel
|
||||||
* Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
|
* Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
|
||||||
|
@ -499,7 +499,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
|
||||||
int pos;
|
int pos;
|
||||||
u32 reg32;
|
u32 reg32;
|
||||||
/*
|
/*
|
||||||
* Some functions in a slot might not all be PCIE functions,
|
* Some functions in a slot might not all be PCIe functions,
|
||||||
* very strange. Disable ASPM for the whole slot
|
* very strange. Disable ASPM for the whole slot
|
||||||
*/
|
*/
|
||||||
list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
|
list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
|
||||||
|
|
|
@ -24,7 +24,7 @@
|
||||||
*/
|
*/
|
||||||
#define DRIVER_VERSION "v1.0"
|
#define DRIVER_VERSION "v1.0"
|
||||||
#define DRIVER_AUTHOR "tom.l.nguyen@intel.com"
|
#define DRIVER_AUTHOR "tom.l.nguyen@intel.com"
|
||||||
#define DRIVER_DESC "PCIE Port Bus Driver"
|
#define DRIVER_DESC "PCIe Port Bus Driver"
|
||||||
MODULE_AUTHOR(DRIVER_AUTHOR);
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
||||||
MODULE_DESCRIPTION(DRIVER_DESC);
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
||||||
MODULE_LICENSE("GPL");
|
MODULE_LICENSE("GPL");
|
||||||
|
|
|
@ -2629,13 +2629,68 @@ static int __init pci_apply_final_quirks(void)
|
||||||
if (!pci_cache_line_size) {
|
if (!pci_cache_line_size) {
|
||||||
printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
|
printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
|
||||||
cls << 2, pci_dfl_cache_line_size << 2);
|
cls << 2, pci_dfl_cache_line_size << 2);
|
||||||
pci_cache_line_size = cls;
|
pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
fs_initcall_sync(pci_apply_final_quirks);
|
fs_initcall_sync(pci_apply_final_quirks);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Followings are device-specific reset methods which can be used to
|
||||||
|
* reset a single function if other methods (e.g. FLR, PM D0->D3) are
|
||||||
|
* not available.
|
||||||
|
*/
|
||||||
|
static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
|
||||||
|
{
|
||||||
|
int pos;
|
||||||
|
|
||||||
|
/* only implement PCI_CLASS_SERIAL_USB at present */
|
||||||
|
if (dev->class == PCI_CLASS_SERIAL_USB) {
|
||||||
|
pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
|
||||||
|
if (!pos)
|
||||||
|
return -ENOTTY;
|
||||||
|
|
||||||
|
if (probe)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
pci_write_config_byte(dev, pos + 0x4, 1);
|
||||||
|
msleep(100);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
} else {
|
||||||
|
return -ENOTTY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
|
||||||
|
{
|
||||||
|
int pos;
|
||||||
|
|
||||||
|
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
||||||
|
if (!pos)
|
||||||
|
return -ENOTTY;
|
||||||
|
|
||||||
|
if (probe)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
|
||||||
|
PCI_EXP_DEVCTL_BCR_FLR);
|
||||||
|
msleep(100);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
|
||||||
|
|
||||||
|
struct pci_dev_reset_methods pci_dev_reset_methods[] = {
|
||||||
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
|
||||||
|
reset_intel_82599_sfp_virtfn },
|
||||||
|
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
|
||||||
|
reset_intel_generic_dev },
|
||||||
|
{ 0 }
|
||||||
|
};
|
||||||
#else
|
#else
|
||||||
void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
|
void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -15,9 +15,9 @@
|
||||||
|
|
||||||
DECLARE_RWSEM(pci_bus_sem);
|
DECLARE_RWSEM(pci_bus_sem);
|
||||||
/*
|
/*
|
||||||
* find the upstream PCIE-to-PCI bridge of a PCI device
|
* find the upstream PCIe-to-PCI bridge of a PCI device
|
||||||
* if the device is PCIE, return NULL
|
* if the device is PCIE, return NULL
|
||||||
* if the device isn't connected to a PCIE bridge (that is its parent is a
|
* if the device isn't connected to a PCIe bridge (that is its parent is a
|
||||||
* legacy PCI bridge and the bridge is directly connected to bus 0), return its
|
* legacy PCI bridge and the bridge is directly connected to bus 0), return its
|
||||||
* parent
|
* parent
|
||||||
*/
|
*/
|
||||||
|
@ -37,7 +37,7 @@ pci_find_upstream_pcie_bridge(struct pci_dev *pdev)
|
||||||
tmp = pdev;
|
tmp = pdev;
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
/* PCI device should connect to a PCIE bridge */
|
/* PCI device should connect to a PCIe bridge */
|
||||||
if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) {
|
if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||||
/* Busted hardware? */
|
/* Busted hardware? */
|
||||||
WARN_ON_ONCE(1);
|
WARN_ON_ONCE(1);
|
||||||
|
|
|
@ -222,7 +222,7 @@ int __ref cb_alloc(struct pcmcia_socket *s)
|
||||||
unsigned int max, pass;
|
unsigned int max, pass;
|
||||||
|
|
||||||
s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
|
s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
|
||||||
/* pcibios_fixup_bus(bus); */
|
pci_fixup_cardbus(bus);
|
||||||
|
|
||||||
max = bus->secondary;
|
max = bus->secondary;
|
||||||
for (pass = 0; pass < 2; pass++)
|
for (pass = 0; pass < 2; pass++)
|
||||||
|
|
|
@ -566,6 +566,9 @@ void pcibios_align_resource(void *, struct resource *, resource_size_t,
|
||||||
resource_size_t);
|
resource_size_t);
|
||||||
void pcibios_update_irq(struct pci_dev *, int irq);
|
void pcibios_update_irq(struct pci_dev *, int irq);
|
||||||
|
|
||||||
|
/* Weak but can be overriden by arch */
|
||||||
|
void pci_fixup_cardbus(struct pci_bus *);
|
||||||
|
|
||||||
/* Generic PCI functions used internally */
|
/* Generic PCI functions used internally */
|
||||||
|
|
||||||
extern struct pci_bus *pci_find_bus(int domain, int busnr);
|
extern struct pci_bus *pci_find_bus(int domain, int busnr);
|
||||||
|
|
Loading…
Reference in a new issue