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Blackfin SPI driver: fix bug SPI DMA incomplete transmission

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SPI writes intermittently drop bytes at end of DMA transfer
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3205
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=2892

Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Bryan Wu 2007-06-11 17:34:17 +08:00
parent 27bb9e79bc
commit d6fe89b063
1 changed files with 10 additions and 5 deletions
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15
drivers/spi/spi_bfin5xx.c
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@ -582,14 +582,19 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
clear_dma_irqstat(CH_SPI);
/* Wait for DMA to complete */
while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN)
continue;
/*
* wait for the last transaction shifted out. yes, these two
* while loops are supposed to be the same (see the HRM).
* wait for the last transaction shifted out. HRM states:
* at this point there may still be data in the SPI DMA FIFO waiting
* to be transmitted ... software needs to poll TXS in the SPI_STAT
* register until it goes low for 2 successive reads
*/
if (drv_data->tx != NULL) {
while (bfin_read_SPI_STAT() & TXS)
continue;
while (bfin_read_SPI_STAT() & TXS)
while ((bfin_read_SPI_STAT() & TXS) ||
(bfin_read_SPI_STAT() & TXS))
continue;
}