MIPS: BMIPS: Let each platform customize the CPU1 IRQ mask
On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1 input, generating spurious IRQs. In this case we want the platform code to be able to mask it off. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8163/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -84,6 +84,7 @@ extern char bmips_smp_int_vec_end;
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extern int bmips_smp_enabled;
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extern int bmips_cpu_offset;
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extern cpumask_t bmips_booted_mask;
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extern unsigned long bmips_tp1_irqs;
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extern void bmips_ebase_setup(void);
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extern asmlinkage void plat_wired_tlb_setup(void);
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@ -43,6 +43,7 @@ static int __maybe_unused max_cpus = 1;
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int bmips_smp_enabled = 1;
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int bmips_cpu_offset;
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cpumask_t bmips_booted_mask;
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unsigned long bmips_tp1_irqs = IE_IRQ1;
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#define RESET_FROM_KSEG0 0x80080800
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#define RESET_FROM_KSEG1 0xa0080800
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@ -257,7 +258,7 @@ static void bmips_smp_finish(void)
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write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
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irq_enable_hazard();
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set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
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set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
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irq_enable_hazard();
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}
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@ -387,7 +388,8 @@ void __ref play_dead(void)
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* IRQ handlers; this clears ST0_IE and returns immediately.
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*/
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clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
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change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
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change_c0_status(
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IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
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IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
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irq_disable_hazard();
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