MIPS: jz4740: Remove obsolete code
This commit removes two things: - The platform_device that corresponds to the RTC driver, since we now probe this driver from devicetree; - The platform power-off code, since all the jz4740-based platforms are now using the jz4740-rtc driver as the system power controller. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Maarten ter Huurne <maarten@treewalker.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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@ -22,7 +22,6 @@
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extern struct platform_device jz4740_udc_device;
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extern struct platform_device jz4740_udc_xceiv_device;
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extern struct platform_device jz4740_mmc_device;
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extern struct platform_device jz4740_rtc_device;
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extern struct platform_device jz4740_i2c_device;
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extern struct platform_device jz4740_nand_device;
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extern struct platform_device jz4740_framebuffer_device;
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@ -88,27 +88,6 @@ struct platform_device jz4740_mmc_device = {
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.resource = jz4740_mmc_resources,
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};
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/* RTC controller */
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static struct resource jz4740_rtc_resources[] = {
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{
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.start = JZ4740_RTC_BASE_ADDR,
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.end = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = JZ4740_IRQ_RTC,
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.end = JZ4740_IRQ_RTC,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device jz4740_rtc_device = {
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.name = "jz4740-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(jz4740_rtc_resources),
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.resource = jz4740_rtc_resources,
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};
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/* I2C controller */
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static struct resource jz4740_i2c_resources[] = {
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{
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@ -57,71 +57,8 @@ static void jz4740_restart(char *command)
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jz4740_halt();
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}
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#define JZ_REG_RTC_CTRL 0x00
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#define JZ_REG_RTC_HIBERNATE 0x20
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#define JZ_REG_RTC_WAKEUP_FILTER 0x24
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#define JZ_REG_RTC_RESET_COUNTER 0x28
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#define JZ_RTC_CTRL_WRDY BIT(7)
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#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
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#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
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static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base)
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{
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uint32_t ctrl;
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do {
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ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
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} while (!(ctrl & JZ_RTC_CTRL_WRDY));
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}
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static void jz4740_power_off(void)
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{
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void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38);
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unsigned long wakeup_filter_ticks;
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unsigned long reset_counter_ticks;
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struct clk *rtc_clk;
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unsigned long rtc_rate;
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rtc_clk = clk_get(NULL, "rtc");
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if (IS_ERR(rtc_clk))
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panic("unable to get RTC clock");
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rtc_rate = clk_get_rate(rtc_clk);
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clk_put(rtc_clk);
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/*
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* Set minimum wakeup pin assertion time: 100 ms.
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* Range is 0 to 2 sec if RTC is clocked at 32 kHz.
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*/
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wakeup_filter_ticks = (100 * rtc_rate) / 1000;
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if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
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wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
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else
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wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
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jz4740_rtc_wait_ready(rtc_base);
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writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER);
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/*
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* Set reset pin low-level assertion time after wakeup: 60 ms.
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* Range is 0 to 125 ms if RTC is clocked at 32 kHz.
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*/
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reset_counter_ticks = (60 * rtc_rate) / 1000;
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if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
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reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
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else
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reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
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jz4740_rtc_wait_ready(rtc_base);
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writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER);
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jz4740_rtc_wait_ready(rtc_base);
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writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
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jz4740_halt();
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}
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void jz4740_reset_init(void)
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{
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_machine_restart = jz4740_restart;
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_machine_halt = jz4740_halt;
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pm_power_off = jz4740_power_off;
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}
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