dmaengine: stm32_mdma: activate pack/unpack feature
If source and destination bus width differs pack/unpack MDMA
feature has to be activated for alignment.
This pack/unpack feature implies to have both source/destination address
and buffer length aligned on bus width.
Fixes: a4ffb13c89
("dmaengine: Add STM32 MDMA driver")
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
parent
f2fd4d9f32
commit
d83f4131c2
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@ -387,14 +387,20 @@ static int stm32_mdma_get_width(struct stm32_mdma_chan *chan,
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}
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}
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static enum dma_slave_buswidth stm32_mdma_get_max_width(u32 buf_len, u32 tlen)
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static enum dma_slave_buswidth stm32_mdma_get_max_width(dma_addr_t addr,
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u32 buf_len, u32 tlen)
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{
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enum dma_slave_buswidth max_width = DMA_SLAVE_BUSWIDTH_8_BYTES;
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for (max_width = DMA_SLAVE_BUSWIDTH_8_BYTES;
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max_width > DMA_SLAVE_BUSWIDTH_1_BYTE;
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max_width >>= 1) {
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if (((buf_len % max_width) == 0) && (tlen >= max_width))
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/*
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* Address and buffer length both have to be aligned on
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* bus width
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*/
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if ((((buf_len | addr) & (max_width - 1)) == 0) &&
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tlen >= max_width)
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break;
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}
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@ -486,7 +492,8 @@ static void stm32_mdma_set_bus(struct stm32_mdma_device *dmadev, u32 *ctbr,
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static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
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enum dma_transfer_direction direction,
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u32 *mdma_ccr, u32 *mdma_ctcr,
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u32 *mdma_ctbr, u32 buf_len)
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u32 *mdma_ctbr, dma_addr_t addr,
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u32 buf_len)
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{
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struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
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struct stm32_mdma_chan_config *chan_config = &chan->chan_config;
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@ -520,6 +527,9 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
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ctcr &= ~STM32_MDMA_CTCR_LEN2_MSK;
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ctcr |= STM32_MDMA_CTCR_TLEN((tlen - 1));
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/* Disable Pack Enable */
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ctcr &= ~STM32_MDMA_CTCR_PKE;
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/* Check burst size constraints */
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if (src_maxburst * src_addr_width > STM32_MDMA_MAX_BURST ||
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dst_maxburst * dst_addr_width > STM32_MDMA_MAX_BURST) {
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@ -551,6 +561,8 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
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switch (direction) {
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case DMA_MEM_TO_DEV:
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dst_addr = chan->dma_config.dst_addr;
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/* Set device data size */
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dst_bus_width = stm32_mdma_get_width(chan, dst_addr_width);
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if (dst_bus_width < 0)
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@ -567,7 +579,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
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ctcr |= STM32_MDMA_CTCR_DBURST((ilog2(dst_best_burst)));
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/* Set memory data size */
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src_addr_width = stm32_mdma_get_max_width(buf_len, tlen);
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src_addr_width = stm32_mdma_get_max_width(addr, buf_len, tlen);
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chan->mem_width = src_addr_width;
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src_bus_width = stm32_mdma_get_width(chan, src_addr_width);
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if (src_bus_width < 0)
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@ -587,15 +599,19 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
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ctcr |= STM32_MDMA_CTCR_SBURST((ilog2(src_best_burst)));
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/* Select bus */
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dst_addr = chan->dma_config.dst_addr;
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stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
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dst_addr);
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if (dst_bus_width != src_bus_width)
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ctcr |= STM32_MDMA_CTCR_PKE;
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/* Set destination address */
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stm32_mdma_write(dmadev, STM32_MDMA_CDAR(chan->id), dst_addr);
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break;
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case DMA_DEV_TO_MEM:
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src_addr = chan->dma_config.src_addr;
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/* Set device data size */
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src_bus_width = stm32_mdma_get_width(chan, src_addr_width);
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if (src_bus_width < 0)
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@ -611,7 +627,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
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ctcr |= STM32_MDMA_CTCR_SBURST((ilog2(src_best_burst)));
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/* Set memory data size */
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dst_addr_width = stm32_mdma_get_max_width(buf_len, tlen);
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dst_addr_width = stm32_mdma_get_max_width(addr, buf_len, tlen);
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chan->mem_width = dst_addr_width;
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dst_bus_width = stm32_mdma_get_width(chan, dst_addr_width);
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if (dst_bus_width < 0)
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@ -630,10 +646,12 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan,
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ctcr |= STM32_MDMA_CTCR_DBURST((ilog2(dst_best_burst)));
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/* Select bus */
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src_addr = chan->dma_config.src_addr;
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stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
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src_addr);
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if (dst_bus_width != src_bus_width)
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ctcr |= STM32_MDMA_CTCR_PKE;
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/* Set source address */
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stm32_mdma_write(dmadev, STM32_MDMA_CSAR(chan->id), src_addr);
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break;
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@ -719,23 +737,27 @@ static int stm32_mdma_setup_xfer(struct stm32_mdma_chan *chan,
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return -EINVAL;
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}
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ret = stm32_mdma_set_xfer_param(chan, direction, &ccr, &ctcr,
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&ctbr, sg_dma_len(sg));
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if (ret < 0)
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return ret;
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if (direction == DMA_MEM_TO_DEV) {
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src_addr = sg_dma_address(sg);
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dst_addr = dma_config->dst_addr;
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ret = stm32_mdma_set_xfer_param(chan, direction, &ccr,
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&ctcr, &ctbr, src_addr,
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sg_dma_len(sg));
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stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
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src_addr);
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} else {
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src_addr = dma_config->src_addr;
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dst_addr = sg_dma_address(sg);
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ret = stm32_mdma_set_xfer_param(chan, direction, &ccr,
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&ctcr, &ctbr, dst_addr,
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sg_dma_len(sg));
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stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
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dst_addr);
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}
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if (ret < 0)
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return ret;
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stm32_mdma_setup_hwdesc(chan, desc, direction, i, src_addr,
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dst_addr, sg_dma_len(sg), ctcr, ctbr,
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i == sg_len - 1, i == 0, false);
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@ -830,8 +852,21 @@ stm32_mdma_prep_dma_cyclic(struct dma_chan *c, dma_addr_t buf_addr,
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if (!desc)
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return NULL;
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ret = stm32_mdma_set_xfer_param(chan, direction, &ccr, &ctcr, &ctbr,
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period_len);
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/* Select bus */
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if (direction == DMA_MEM_TO_DEV) {
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src_addr = buf_addr;
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ret = stm32_mdma_set_xfer_param(chan, direction, &ccr, &ctcr,
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&ctbr, src_addr, period_len);
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stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
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src_addr);
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} else {
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dst_addr = buf_addr;
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ret = stm32_mdma_set_xfer_param(chan, direction, &ccr, &ctcr,
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&ctbr, dst_addr, period_len);
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stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
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dst_addr);
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}
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if (ret < 0)
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goto xfer_setup_err;
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@ -840,17 +875,6 @@ stm32_mdma_prep_dma_cyclic(struct dma_chan *c, dma_addr_t buf_addr,
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ccr |= STM32_MDMA_CCR_TEIE | STM32_MDMA_CCR_CTCIE | STM32_MDMA_CCR_BTIE;
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desc->ccr = ccr;
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/* Select bus */
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if (direction == DMA_MEM_TO_DEV) {
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src_addr = buf_addr;
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stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
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src_addr);
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} else {
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dst_addr = buf_addr;
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stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
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dst_addr);
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}
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/* Configure hwdesc list */
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for (i = 0; i < count; i++) {
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if (direction == DMA_MEM_TO_DEV) {
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@ -956,9 +980,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
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ctcr |= STM32_MDMA_CTCR_TLEN((tlen - 1));
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/* Set source best burst size */
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max_width = stm32_mdma_get_max_width(len, tlen);
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if (src % max_width)
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max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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max_width = stm32_mdma_get_max_width(src, len, tlen);
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src_bus_width = stm32_mdma_get_width(chan, max_width);
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max_burst = tlen / max_width;
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@ -971,9 +993,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
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STM32_MDMA_CTCR_SINCOS(src_bus_width);
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/* Set destination best burst size */
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max_width = stm32_mdma_get_max_width(len, tlen);
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if (dest % max_width)
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max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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max_width = stm32_mdma_get_max_width(dest, len, tlen);
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dst_bus_width = stm32_mdma_get_width(chan, max_width);
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max_burst = tlen / max_width;
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@ -1014,9 +1034,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
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STM32_MDMA_MAX_BLOCK_LEN);
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/* Set source best burst size */
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max_width = stm32_mdma_get_max_width(len, tlen);
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if (src % max_width)
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max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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max_width = stm32_mdma_get_max_width(src, len, tlen);
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src_bus_width = stm32_mdma_get_width(chan, max_width);
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max_burst = tlen / max_width;
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@ -1030,9 +1048,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
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STM32_MDMA_CTCR_SINCOS(src_bus_width);
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/* Set destination best burst size */
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max_width = stm32_mdma_get_max_width(len, tlen);
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if (dest % max_width)
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max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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max_width = stm32_mdma_get_max_width(dest, len, tlen);
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dst_bus_width = stm32_mdma_get_width(chan, max_width);
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max_burst = tlen / max_width;
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