From d8664979e6ba97024c43d6248f94982ee0c8d1ee Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 25 Mar 2015 14:25:34 -0600 Subject: [PATCH] ARM: dts: qcom: Add idle states device nodes for 8084 Add ARM common idle states device bindings for cpuidle support for APQ 8084. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer Signed-off-by: Kumar Gala Signed-off-by: Olof Johansson --- arch/arm/boot/dts/qcom-apq8084.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index df2e308d06d3..7084010ee61b 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -22,6 +22,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -32,6 +33,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -42,6 +44,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -52,6 +55,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { @@ -59,6 +63,16 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu {