Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into fixes
This commit is contained in:
commit
d8cff1365e
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@ -180,7 +180,7 @@ static const uint32_t mx25pdk_keymap[] = {
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KEY(3, 3, KEY_POWER),
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KEY(3, 3, KEY_POWER),
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};
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};
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static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = {
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static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
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.keymap = mx25pdk_keymap,
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.keymap = mx25pdk_keymap,
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.keymap_size = ARRAY_SIZE(mx25pdk_keymap),
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.keymap_size = ARRAY_SIZE(mx25pdk_keymap),
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};
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};
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@ -304,7 +304,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
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reg &= ~BM_CLKCTRL_##dr##_DIV; \
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reg &= ~BM_CLKCTRL_##dr##_DIV; \
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reg |= div << BP_CLKCTRL_##dr##_DIV; \
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reg |= div << BP_CLKCTRL_##dr##_DIV; \
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if (reg | (1 << clk->enable_shift)) { \
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if (reg & (1 << clk->enable_shift)) { \
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pr_err("%s: clock is gated\n", __func__); \
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pr_err("%s: clock is gated\n", __func__); \
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return -EINVAL; \
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return -EINVAL; \
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} \
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} \
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@ -347,7 +347,7 @@ static int name##_set_parent(struct clk *clk, struct clk *parent) \
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{ \
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{ \
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if (parent != clk->parent) { \
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if (parent != clk->parent) { \
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__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
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__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
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HW_CLKCTRL_CLKSEQ_TOG); \
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
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clk->parent = parent; \
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clk->parent = parent; \
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} \
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} \
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\
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\
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@ -355,12 +355,12 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
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} else { \
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} else { \
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reg &= ~BM_CLKCTRL_##dr##_DIV; \
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reg &= ~BM_CLKCTRL_##dr##_DIV; \
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reg |= div << BP_CLKCTRL_##dr##_DIV; \
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reg |= div << BP_CLKCTRL_##dr##_DIV; \
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if (reg | (1 << clk->enable_shift)) { \
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if (reg & (1 << clk->enable_shift)) { \
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pr_err("%s: clock is gated\n", __func__); \
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pr_err("%s: clock is gated\n", __func__); \
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return -EINVAL; \
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return -EINVAL; \
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} \
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} \
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} \
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} \
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__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); \
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__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
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\
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\
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for (i = 10000; i; i--) \
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for (i = 10000; i; i--) \
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if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
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if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
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@ -483,7 +483,7 @@ static int name##_set_parent(struct clk *clk, struct clk *parent) \
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{ \
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{ \
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if (parent != clk->parent) { \
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if (parent != clk->parent) { \
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__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
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__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
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HW_CLKCTRL_CLKSEQ_TOG); \
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
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clk->parent = parent; \
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clk->parent = parent; \
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} \
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} \
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\
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\
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@ -609,7 +609,6 @@ static struct clk_lookup lookups[] = {
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_REGISTER_CLOCK("duart", NULL, uart_clk)
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_REGISTER_CLOCK("duart", NULL, uart_clk)
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_REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
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_REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
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_REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
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_REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
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_REGISTER_CLOCK("fec.0", NULL, fec_clk)
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_REGISTER_CLOCK("rtc", NULL, rtc_clk)
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_REGISTER_CLOCK("rtc", NULL, rtc_clk)
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_REGISTER_CLOCK("pll2", NULL, pll2_clk)
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_REGISTER_CLOCK("pll2", NULL, pll2_clk)
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_REGISTER_CLOCK(NULL, "hclk", hbus_clk)
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_REGISTER_CLOCK(NULL, "hclk", hbus_clk)
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@ -57,7 +57,6 @@ static void __clk_disable(struct clk *clk)
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if (clk->disable)
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if (clk->disable)
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clk->disable(clk);
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clk->disable(clk);
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__clk_disable(clk->parent);
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__clk_disable(clk->parent);
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__clk_disable(clk->secondary);
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}
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}
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}
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}
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@ -68,7 +67,6 @@ static int __clk_enable(struct clk *clk)
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if (clk->usecount++ == 0) {
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if (clk->usecount++ == 0) {
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__clk_enable(clk->parent);
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__clk_enable(clk->parent);
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__clk_enable(clk->secondary);
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if (clk->enable)
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if (clk->enable)
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clk->enable(clk);
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clk->enable(clk);
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@ -139,6 +139,8 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
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struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
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u32 gpio_irq_no_base = port->virtual_irq_start;
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u32 gpio_irq_no_base = port->virtual_irq_start;
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
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irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
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__raw_readl(port->base + PINCTRL_IRQEN(port->id));
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__raw_readl(port->base + PINCTRL_IRQEN(port->id));
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@ -29,8 +29,6 @@ struct clk {
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int id;
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int id;
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/* Source clock this clk depends on */
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/* Source clock this clk depends on */
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struct clk *parent;
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struct clk *parent;
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/* Secondary clock to enable/disable with this clock */
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struct clk *secondary;
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/* Reference count of clock enable/disable */
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/* Reference count of clock enable/disable */
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__s8 usecount;
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__s8 usecount;
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/* Register bit position for clock's enable/disable control. */
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/* Register bit position for clock's enable/disable control. */
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@ -95,6 +95,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
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case MACH_TYPE_MX35_3DS:
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case MACH_TYPE_MX35_3DS:
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case MACH_TYPE_PCM043:
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case MACH_TYPE_PCM043:
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case MACH_TYPE_LILLY1131:
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case MACH_TYPE_LILLY1131:
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case MACH_TYPE_VPR200:
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uart_base = MX3X_UART1_BASE_ADDR;
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uart_base = MX3X_UART1_BASE_ADDR;
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break;
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break;
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case MACH_TYPE_MAGX_ZN5:
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case MACH_TYPE_MAGX_ZN5:
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@ -102,6 +103,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
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break;
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break;
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case MACH_TYPE_MX51_BABBAGE:
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case MACH_TYPE_MX51_BABBAGE:
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case MACH_TYPE_EUKREA_CPUIMX51SD:
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case MACH_TYPE_EUKREA_CPUIMX51SD:
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case MACH_TYPE_MX51_3DS:
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uart_base = MX51_UART1_BASE_ADDR;
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uart_base = MX51_UART1_BASE_ADDR;
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break;
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break;
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case MACH_TYPE_MX50_RDP:
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case MACH_TYPE_MX50_RDP:
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