[ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK
All current Simtec designs source the DCLK outputs from the UPLL. This means the DCLK's parent must be set to UPLL so that anything enabling and disabling an UPLL sourced clock does not shutdown the DCLK due to missing open counts. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1017be88d3
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d96a980441
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@ -592,10 +592,10 @@ static void __init bast_map_io(void)
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{
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{
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/* initialise the clocks */
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/* initialise the clocks */
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s3c24xx_dclk0.parent = NULL;
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s3c24xx_dclk0.parent = &clk_upll;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk1.parent = NULL;
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s3c24xx_dclk1.parent = &clk_upll;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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@ -393,7 +393,7 @@ static void __init vr1000_map_io(void)
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{
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{
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/* initialise clock sources */
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/* initialise clock sources */
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s3c24xx_dclk0.parent = NULL;
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s3c24xx_dclk0.parent = &clk_upll;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk1.parent = NULL;
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s3c24xx_dclk1.parent = NULL;
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@ -413,10 +413,10 @@ static void __init anubis_map_io(void)
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{
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{
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/* initialise the clocks */
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/* initialise the clocks */
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s3c24xx_dclk0.parent = NULL;
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s3c24xx_dclk0.parent = &clk_upll;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk1.parent = NULL;
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s3c24xx_dclk1.parent = &clk_upll;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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@ -18,6 +18,7 @@
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#include <linux/device.h>
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#include <linux/device.h>
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#include <linux/sysdev.h>
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <linux/serial_core.h>
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#include <linux/clk.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/map.h>
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@ -344,10 +345,10 @@ static void __init osiris_map_io(void)
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/* initialise the clocks */
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/* initialise the clocks */
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s3c24xx_dclk0.parent = NULL;
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s3c24xx_dclk0.parent = &clk_upll;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk1.parent = NULL;
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s3c24xx_dclk1.parent = &clk_upll;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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