pinctrl: exynos: Add driver data for Exynos3250
This patch adds driver data (bank list and EINT layout) for Exynos3250 to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output ports. There are 23 general port groups. Changes from v1: - Add signed-off of sender - Post only separated patch for pinctrl from following patchset(v1) : https://lkml.org/lkml/2014/4/10/286 Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -718,6 +718,73 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
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},
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};
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/* pin banks of exynos3250 pin-controller 0 */
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static struct samsung_pin_bank exynos3250_pin_banks0[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
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EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
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EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
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EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
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EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
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EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
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};
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/* pin banks of exynos3250 pin-controller 1 */
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static struct samsung_pin_bank exynos3250_pin_banks1[] = {
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EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
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EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
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EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
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EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
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EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
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EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
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EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
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EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
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EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
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EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
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EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
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EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
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EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
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EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
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EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
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};
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/*
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* Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
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* two gpio/pin-mux/pinconfig controllers.
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*/
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struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
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{
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/* pin-controller instance 0 data */
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.pin_banks = exynos3250_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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.label = "exynos3250-gpio-ctrl0",
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}, {
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/* pin-controller instance 1 data */
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.pin_banks = exynos3250_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.weint_con = EXYNOS_WKUP_ECON_OFFSET,
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.weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
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.weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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.label = "exynos3250-gpio-ctrl1",
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},
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};
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/* pin banks of exynos4210 pin-controller 0 */
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static struct samsung_pin_bank exynos4210_pin_banks0[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
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@ -1114,6 +1114,8 @@ static struct syscore_ops samsung_pinctrl_syscore_ops = {
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static const struct of_device_id samsung_pinctrl_dt_match[] = {
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#ifdef CONFIG_PINCTRL_EXYNOS
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{ .compatible = "samsung,exynos3250-pinctrl",
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.data = (void *)exynos3250_pin_ctrl },
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{ .compatible = "samsung,exynos4210-pinctrl",
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.data = (void *)exynos4210_pin_ctrl },
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{ .compatible = "samsung,exynos4x12-pinctrl",
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@ -251,6 +251,7 @@ struct samsung_pmx_func {
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};
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/* list of all exported SoC specific data */
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extern struct samsung_pin_ctrl exynos3250_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
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