spi: spi-ep93xx: use the default master transfer queueing mechanism
Update this driver to the default implementation of transfer_one_message(). Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Mark Brown <broonie@kernel.org>zero-colors
H Hartley Sweeten
Mark Brown
parent
c7a909cf25
commit
d9a017713d
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@ -73,7 +73,6 @@
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* @clk: clock for the controller
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* @mmio: pointer to ioremap()'d registers
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* @sspdr_phys: physical address of the SSPDR register
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* @wait: wait here until given transfer is completed
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* @tx: current byte in transfer to transmit
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* @rx: current byte in transfer to receive
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* @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
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@ -91,7 +90,6 @@ struct ep93xx_spi {
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struct clk *clk;
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void __iomem *mmio;
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unsigned long sspdr_phys;
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struct completion wait;
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size_t tx;
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size_t rx;
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size_t fifo_level;
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@ -123,8 +121,7 @@ static int ep93xx_spi_calc_divisors(struct spi_master *master,
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/*
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* Make sure that max value is between values supported by the
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* controller. Note that minimum value is already checked in
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* ep93xx_spi_transfer_one_message().
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* controller.
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*/
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rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
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@ -149,15 +146,6 @@ static int ep93xx_spi_calc_divisors(struct spi_master *master,
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return -EINVAL;
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}
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static void ep93xx_spi_cs_control(struct spi_device *spi, bool enable)
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{
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if (spi->mode & SPI_CS_HIGH)
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enable = !enable;
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if (gpio_is_valid(spi->cs_gpio))
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gpio_set_value(spi->cs_gpio, !enable);
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}
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static int ep93xx_spi_chip_setup(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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@ -188,34 +176,38 @@ static int ep93xx_spi_chip_setup(struct spi_master *master,
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return 0;
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}
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static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
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static void ep93xx_do_write(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *xfer = master->cur_msg->state;
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u32 val = 0;
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if (t->bits_per_word > 8) {
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if (t->tx_buf)
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val = ((u16 *)t->tx_buf)[espi->tx];
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if (xfer->bits_per_word > 8) {
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if (xfer->tx_buf)
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val = ((u16 *)xfer->tx_buf)[espi->tx];
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espi->tx += 2;
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} else {
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if (t->tx_buf)
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val = ((u8 *)t->tx_buf)[espi->tx];
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if (xfer->tx_buf)
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val = ((u8 *)xfer->tx_buf)[espi->tx];
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espi->tx += 1;
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}
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writel(val, espi->mmio + SSPDR);
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}
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static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
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static void ep93xx_do_read(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *xfer = master->cur_msg->state;
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u32 val;
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val = readl(espi->mmio + SSPDR);
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if (t->bits_per_word > 8) {
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if (t->rx_buf)
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((u16 *)t->rx_buf)[espi->rx] = val;
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if (xfer->bits_per_word > 8) {
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if (xfer->rx_buf)
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((u16 *)xfer->rx_buf)[espi->rx] = val;
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espi->rx += 2;
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} else {
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if (t->rx_buf)
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((u8 *)t->rx_buf)[espi->rx] = val;
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if (xfer->rx_buf)
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((u8 *)xfer->rx_buf)[espi->rx] = val;
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espi->rx += 1;
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}
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}
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@ -234,45 +226,26 @@ static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
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static int ep93xx_spi_read_write(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *t = master->cur_msg->state;
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struct spi_transfer *xfer = master->cur_msg->state;
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/* read as long as RX FIFO has frames in it */
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while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
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ep93xx_do_read(espi, t);
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ep93xx_do_read(master);
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espi->fifo_level--;
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}
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/* write as long as TX FIFO has room */
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while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
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ep93xx_do_write(espi, t);
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while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {
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ep93xx_do_write(master);
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espi->fifo_level++;
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}
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if (espi->rx == t->len)
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if (espi->rx == xfer->len)
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return 0;
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return -EINPROGRESS;
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}
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static void ep93xx_spi_pio_transfer(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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/*
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* Now everything is set up for the current transfer. We prime the TX
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* FIFO, enable interrupts, and wait for the transfer to complete.
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*/
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if (ep93xx_spi_read_write(master)) {
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u32 val;
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val = readl(espi->mmio + SSPCR1);
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val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
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writel(val, espi->mmio + SSPCR1);
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wait_for_completion(&espi->wait);
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}
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}
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/**
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* ep93xx_spi_dma_prepare() - prepares a DMA transfer
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* @master: SPI master
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@ -287,7 +260,7 @@ ep93xx_spi_dma_prepare(struct spi_master *master,
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enum dma_transfer_direction dir)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *t = master->cur_msg->state;
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struct spi_transfer *xfer = master->cur_msg->state;
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struct dma_async_tx_descriptor *txd;
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enum dma_slave_buswidth buswidth;
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struct dma_slave_config conf;
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@ -295,10 +268,10 @@ ep93xx_spi_dma_prepare(struct spi_master *master,
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struct sg_table *sgt;
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struct dma_chan *chan;
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const void *buf, *pbuf;
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size_t len = t->len;
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size_t len = xfer->len;
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int i, ret, nents;
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if (t->bits_per_word > 8)
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if (xfer->bits_per_word > 8)
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buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
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else
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buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
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@ -308,14 +281,14 @@ ep93xx_spi_dma_prepare(struct spi_master *master,
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if (dir == DMA_DEV_TO_MEM) {
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chan = espi->dma_rx;
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buf = t->rx_buf;
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buf = xfer->rx_buf;
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sgt = &espi->rx_sgt;
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conf.src_addr = espi->sspdr_phys;
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conf.src_addr_width = buswidth;
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} else {
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chan = espi->dma_tx;
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buf = t->tx_buf;
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buf = xfer->tx_buf;
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sgt = &espi->tx_sgt;
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conf.dst_addr = espi->sspdr_phys;
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@ -406,10 +379,15 @@ static void ep93xx_spi_dma_finish(struct spi_master *master,
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static void ep93xx_spi_dma_callback(void *callback_param)
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{
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complete(callback_param);
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struct spi_master *master = callback_param;
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ep93xx_spi_dma_finish(master, DMA_MEM_TO_DEV);
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ep93xx_spi_dma_finish(master, DMA_DEV_TO_MEM);
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spi_finalize_current_transfer(master);
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}
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static void ep93xx_spi_dma_transfer(struct spi_master *master)
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static int ep93xx_spi_dma_transfer(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct dma_async_tx_descriptor *rxd, *txd;
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@ -417,177 +395,29 @@ static void ep93xx_spi_dma_transfer(struct spi_master *master)
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rxd = ep93xx_spi_dma_prepare(master, DMA_DEV_TO_MEM);
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if (IS_ERR(rxd)) {
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dev_err(&master->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
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master->cur_msg->status = PTR_ERR(rxd);
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return;
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return PTR_ERR(rxd);
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}
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txd = ep93xx_spi_dma_prepare(master, DMA_MEM_TO_DEV);
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if (IS_ERR(txd)) {
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ep93xx_spi_dma_finish(master, DMA_DEV_TO_MEM);
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dev_err(&master->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
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master->cur_msg->status = PTR_ERR(txd);
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return;
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return PTR_ERR(txd);
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}
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/* We are ready when RX is done */
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rxd->callback = ep93xx_spi_dma_callback;
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rxd->callback_param = &espi->wait;
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rxd->callback_param = master;
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/* Now submit both descriptors and wait while they finish */
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/* Now submit both descriptors and start DMA */
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dmaengine_submit(rxd);
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dmaengine_submit(txd);
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dma_async_issue_pending(espi->dma_rx);
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dma_async_issue_pending(espi->dma_tx);
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wait_for_completion(&espi->wait);
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ep93xx_spi_dma_finish(master, DMA_MEM_TO_DEV);
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ep93xx_spi_dma_finish(master, DMA_DEV_TO_MEM);
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}
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/**
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* ep93xx_spi_process_transfer() - processes one SPI transfer
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* @master: SPI master
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* @msg: current message
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* @t: transfer to process
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*
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* This function processes one SPI transfer given in @t. Function waits until
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* transfer is complete (may sleep) and updates @msg->status based on whether
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* transfer was successfully processed or not.
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*/
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static void ep93xx_spi_process_transfer(struct spi_master *master,
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struct spi_message *msg,
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struct spi_transfer *t)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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int err;
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msg->state = t;
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err = ep93xx_spi_chip_setup(master, msg->spi, t);
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if (err) {
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dev_err(&master->dev,
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"failed to setup chip for transfer\n");
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msg->status = err;
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return;
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}
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espi->rx = 0;
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espi->tx = 0;
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/*
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* There is no point of setting up DMA for the transfers which will
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* fit into the FIFO and can be transferred with a single interrupt.
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* So in these cases we will be using PIO and don't bother for DMA.
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*/
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if (espi->dma_rx && t->len > SPI_FIFO_SIZE)
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ep93xx_spi_dma_transfer(master);
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else
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ep93xx_spi_pio_transfer(master);
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/*
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* In case of error during transmit, we bail out from processing
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* the message.
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*/
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if (msg->status)
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return;
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msg->actual_length += t->len;
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/*
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* After this transfer is finished, perform any possible
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* post-transfer actions requested by the protocol driver.
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*/
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if (t->delay_usecs) {
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set_current_state(TASK_UNINTERRUPTIBLE);
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schedule_timeout(usecs_to_jiffies(t->delay_usecs));
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}
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if (t->cs_change) {
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if (!list_is_last(&t->transfer_list, &msg->transfers)) {
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/*
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* In case protocol driver is asking us to drop the
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* chipselect briefly, we let the scheduler to handle
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* any "delay" here.
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*/
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ep93xx_spi_cs_control(msg->spi, false);
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cond_resched();
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ep93xx_spi_cs_control(msg->spi, true);
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}
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}
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}
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/*
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* ep93xx_spi_process_message() - process one SPI message
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* @master: SPI master
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* @msg: message to process
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*
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* This function processes a single SPI message. We go through all transfers in
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* the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
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* asserted during the whole message (unless per transfer cs_change is set).
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*
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* @msg->status contains %0 in case of success or negative error code in case of
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* failure.
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*/
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static void ep93xx_spi_process_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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unsigned long timeout;
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struct spi_transfer *t;
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/*
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* Just to be sure: flush any data from RX FIFO.
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*/
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timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
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while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
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if (time_after(jiffies, timeout)) {
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dev_warn(&master->dev,
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"timeout while flushing RX FIFO\n");
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msg->status = -ETIMEDOUT;
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return;
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}
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readl(espi->mmio + SSPDR);
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}
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/*
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* We explicitly handle FIFO level. This way we don't have to check TX
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* FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
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*/
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espi->fifo_level = 0;
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/*
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* Assert the chipselect.
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*/
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ep93xx_spi_cs_control(msg->spi, true);
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list_for_each_entry(t, &msg->transfers, transfer_list) {
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ep93xx_spi_process_transfer(master, msg, t);
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if (msg->status)
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break;
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}
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/*
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* Now the whole message is transferred (or failed for some reason). We
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* deselect the device and disable the SPI controller.
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*/
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ep93xx_spi_cs_control(msg->spi, false);
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}
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static int ep93xx_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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msg->state = NULL;
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msg->status = 0;
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msg->actual_length = 0;
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ep93xx_spi_process_message(master, msg);
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spi_finalize_current_message(master);
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return 0;
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/* signal that we need to wait for completion */
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return 1;
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}
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static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
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@ -630,11 +460,76 @@ static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
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val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
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writel(val, espi->mmio + SSPCR1);
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complete(&espi->wait);
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spi_finalize_current_transfer(master);
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return IRQ_HANDLED;
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}
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static int ep93xx_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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u32 val;
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int ret;
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ret = ep93xx_spi_chip_setup(master, spi, xfer);
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if (ret) {
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dev_err(&master->dev, "failed to setup chip for transfer\n");
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return ret;
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}
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master->cur_msg->state = xfer;
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espi->rx = 0;
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espi->tx = 0;
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/*
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* There is no point of setting up DMA for the transfers which will
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* fit into the FIFO and can be transferred with a single interrupt.
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* So in these cases we will be using PIO and don't bother for DMA.
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*/
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if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)
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return ep93xx_spi_dma_transfer(master);
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/* Using PIO so prime the TX FIFO and enable interrupts */
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ep93xx_spi_read_write(master);
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val = readl(espi->mmio + SSPCR1);
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val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
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writel(val, espi->mmio + SSPCR1);
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/* signal that we need to wait for completion */
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return 1;
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}
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static int ep93xx_spi_prepare_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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unsigned long timeout;
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/*
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* Just to be sure: flush any data from RX FIFO.
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*/
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||||
timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
|
||||
while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
|
||||
if (time_after(jiffies, timeout)) {
|
||||
dev_warn(&master->dev,
|
||||
"timeout while flushing RX FIFO\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
readl(espi->mmio + SSPDR);
|
||||
}
|
||||
|
||||
/*
|
||||
* We explicitly handle FIFO level. This way we don't have to check TX
|
||||
* FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
|
||||
*/
|
||||
espi->fifo_level = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ep93xx_spi_prepare_hardware(struct spi_master *master)
|
||||
{
|
||||
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
||||
|
|
@ -769,7 +664,8 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
|
|||
|
||||
master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;
|
||||
master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;
|
||||
master->transfer_one_message = ep93xx_spi_transfer_one_message;
|
||||
master->prepare_message = ep93xx_spi_prepare_message;
|
||||
master->transfer_one = ep93xx_spi_transfer_one;
|
||||
master->bus_num = pdev->id;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
|
||||
|
|
@ -810,8 +706,6 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
|
|||
goto fail_release_master;
|
||||
}
|
||||
|
||||
init_completion(&espi->wait);
|
||||
|
||||
/*
|
||||
* Calculate maximum and minimum supported clock rates
|
||||
* for the controller.
|
||||
|
|
|
|||
Loading…
Reference in New Issue