pinctrl: ocelot: add MSCC Jaguar2 support
Jaguar2 has the same register layout as Ocelot but it has 64 pins, meaning that there are 2 registers instead of one. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
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a49d784d5a
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da801ab56a
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@ -2,7 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings
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----------------------------------------------------
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Required properties:
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- compatible : Should be "mscc,ocelot-pinctrl"
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- compatible : Should be "mscc,ocelot-pinctrl" or
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"mscc,jaguar2-pinctrl"
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- reg : Address and length of the register set for the device
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- gpio-controller : Indicates this device is a GPIO controller
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- #gpio-cells : Must be 2.
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@ -350,15 +350,14 @@ config PINCTRL_RK805
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This selects the pinctrl driver for RK805.
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config PINCTRL_OCELOT
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bool "Pinctrl driver for the Microsemi Ocelot SoCs"
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default y
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bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
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depends on OF
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depends on MSCC_OCELOT || COMPILE_TEST
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select GENERIC_PINCONF
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select GENERIC_PINCTRL_GROUPS
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select GENERIC_PINMUX_FUNCTIONS
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select OF_GPIO
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select REGMAP_MMIO
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source "drivers/pinctrl/actions/Kconfig"
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@ -37,7 +37,6 @@
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#define OCELOT_GPIO_ALT1 0x24
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#define OCELOT_GPIO_SD_MAP 0x28
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#define OCELOT_PINS 22
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#define OCELOT_FUNC_PER_PIN 4
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enum {
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@ -48,6 +47,7 @@ enum {
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FUNC_IRQ1_IN,
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FUNC_IRQ1_OUT,
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FUNC_MIIM1,
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FUNC_MIIM2,
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FUNC_PCI_WAKE,
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FUNC_PTP0,
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FUNC_PTP1,
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@ -62,10 +62,23 @@ enum {
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FUNC_SFP3,
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FUNC_SFP4,
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FUNC_SFP5,
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FUNC_SFP6,
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FUNC_SFP7,
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FUNC_SFP8,
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FUNC_SFP9,
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FUNC_SFP10,
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FUNC_SFP11,
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FUNC_SFP12,
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FUNC_SFP13,
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FUNC_SFP14,
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FUNC_SFP15,
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FUNC_SG0,
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FUNC_SG1,
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FUNC_SG2,
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FUNC_SI,
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FUNC_TACHO,
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FUNC_TWI,
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FUNC_TWI2,
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FUNC_TWI_SCL_M,
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FUNC_UART,
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FUNC_UART2,
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@ -80,6 +93,7 @@ static const char *const ocelot_function_names[] = {
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[FUNC_IRQ1_IN] = "irq1_in",
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[FUNC_IRQ1_OUT] = "irq1_out",
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[FUNC_MIIM1] = "miim1",
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[FUNC_MIIM2] = "miim2",
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[FUNC_PCI_WAKE] = "pci_wake",
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[FUNC_PTP0] = "ptp0",
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[FUNC_PTP1] = "ptp1",
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@ -94,10 +108,23 @@ static const char *const ocelot_function_names[] = {
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[FUNC_SFP3] = "sfp3",
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[FUNC_SFP4] = "sfp4",
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[FUNC_SFP5] = "sfp5",
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[FUNC_SFP6] = "sfp6",
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[FUNC_SFP7] = "sfp7",
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[FUNC_SFP8] = "sfp8",
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[FUNC_SFP9] = "sfp9",
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[FUNC_SFP10] = "sfp10",
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[FUNC_SFP11] = "sfp11",
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[FUNC_SFP12] = "sfp12",
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[FUNC_SFP13] = "sfp13",
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[FUNC_SFP14] = "sfp14",
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[FUNC_SFP15] = "sfp15",
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[FUNC_SG0] = "sg0",
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[FUNC_SG1] = "sg1",
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[FUNC_SG2] = "sg2",
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[FUNC_SI] = "si",
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[FUNC_TACHO] = "tacho",
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[FUNC_TWI] = "twi",
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[FUNC_TWI2] = "twi2",
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[FUNC_TWI_SCL_M] = "twi_scl_m",
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[FUNC_UART] = "uart",
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[FUNC_UART2] = "uart2",
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@ -118,7 +145,9 @@ struct ocelot_pinctrl {
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struct pinctrl_dev *pctl;
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struct gpio_chip gpio_chip;
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struct regmap *map;
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struct pinctrl_desc *desc;
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struct ocelot_pmx_func func[FUNC_MAX];
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u8 stride;
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};
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#define OCELOT_P(p, f0, f1, f2) \
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@ -183,6 +212,152 @@ static const struct pinctrl_pin_desc ocelot_pins[] = {
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OCELOT_PIN(21),
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};
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#define JAGUAR2_P(p, f0, f1) \
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static struct ocelot_pin_caps jaguar2_pin_##p = { \
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.pin = p, \
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.functions = { \
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FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
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}, \
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}
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JAGUAR2_P(0, SG0, NONE);
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JAGUAR2_P(1, SG0, NONE);
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JAGUAR2_P(2, SG0, NONE);
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JAGUAR2_P(3, SG0, NONE);
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JAGUAR2_P(4, SG1, NONE);
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JAGUAR2_P(5, SG1, NONE);
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JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
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JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
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JAGUAR2_P(8, PTP0, NONE);
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JAGUAR2_P(9, PTP1, NONE);
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JAGUAR2_P(10, UART, NONE);
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JAGUAR2_P(11, UART, NONE);
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JAGUAR2_P(12, SG1, NONE);
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JAGUAR2_P(13, SG1, NONE);
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JAGUAR2_P(14, TWI, TWI_SCL_M);
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JAGUAR2_P(15, TWI, NONE);
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JAGUAR2_P(16, SI, TWI_SCL_M);
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JAGUAR2_P(17, SI, TWI_SCL_M);
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JAGUAR2_P(18, SI, TWI_SCL_M);
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JAGUAR2_P(19, PCI_WAKE, NONE);
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JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
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JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
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JAGUAR2_P(22, TACHO, NONE);
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JAGUAR2_P(23, PWM, NONE);
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JAGUAR2_P(24, UART2, NONE);
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JAGUAR2_P(25, UART2, SI);
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JAGUAR2_P(26, PTP2, SI);
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JAGUAR2_P(27, PTP3, SI);
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JAGUAR2_P(28, TWI2, SI);
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JAGUAR2_P(29, TWI2, SI);
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JAGUAR2_P(30, SG2, SI);
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JAGUAR2_P(31, SG2, SI);
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JAGUAR2_P(32, SG2, SI);
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JAGUAR2_P(33, SG2, SI);
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JAGUAR2_P(34, NONE, TWI_SCL_M);
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JAGUAR2_P(35, NONE, TWI_SCL_M);
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JAGUAR2_P(36, NONE, TWI_SCL_M);
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JAGUAR2_P(37, NONE, TWI_SCL_M);
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JAGUAR2_P(38, NONE, TWI_SCL_M);
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JAGUAR2_P(39, NONE, TWI_SCL_M);
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JAGUAR2_P(40, NONE, TWI_SCL_M);
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JAGUAR2_P(41, NONE, TWI_SCL_M);
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JAGUAR2_P(42, NONE, TWI_SCL_M);
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JAGUAR2_P(43, NONE, TWI_SCL_M);
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JAGUAR2_P(44, NONE, SFP8);
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JAGUAR2_P(45, NONE, SFP9);
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JAGUAR2_P(46, NONE, SFP10);
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JAGUAR2_P(47, NONE, SFP11);
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JAGUAR2_P(48, SFP0, NONE);
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JAGUAR2_P(49, SFP1, SI);
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JAGUAR2_P(50, SFP2, SI);
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JAGUAR2_P(51, SFP3, SI);
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JAGUAR2_P(52, SFP4, NONE);
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JAGUAR2_P(53, SFP5, NONE);
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JAGUAR2_P(54, SFP6, NONE);
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JAGUAR2_P(55, SFP7, NONE);
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JAGUAR2_P(56, MIIM1, SFP12);
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JAGUAR2_P(57, MIIM1, SFP13);
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JAGUAR2_P(58, MIIM2, SFP14);
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JAGUAR2_P(59, MIIM2, SFP15);
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JAGUAR2_P(60, NONE, NONE);
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JAGUAR2_P(61, NONE, NONE);
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JAGUAR2_P(62, NONE, NONE);
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JAGUAR2_P(63, NONE, NONE);
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#define JAGUAR2_PIN(n) { \
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.number = n, \
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.name = "GPIO_"#n, \
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.drv_data = &jaguar2_pin_##n \
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}
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static const struct pinctrl_pin_desc jaguar2_pins[] = {
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JAGUAR2_PIN(0),
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JAGUAR2_PIN(1),
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JAGUAR2_PIN(2),
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JAGUAR2_PIN(3),
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JAGUAR2_PIN(4),
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JAGUAR2_PIN(5),
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JAGUAR2_PIN(6),
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JAGUAR2_PIN(7),
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JAGUAR2_PIN(8),
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JAGUAR2_PIN(9),
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JAGUAR2_PIN(10),
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JAGUAR2_PIN(11),
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JAGUAR2_PIN(12),
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JAGUAR2_PIN(13),
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JAGUAR2_PIN(14),
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JAGUAR2_PIN(15),
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JAGUAR2_PIN(16),
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JAGUAR2_PIN(17),
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JAGUAR2_PIN(18),
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JAGUAR2_PIN(19),
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JAGUAR2_PIN(20),
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JAGUAR2_PIN(21),
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JAGUAR2_PIN(22),
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JAGUAR2_PIN(23),
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JAGUAR2_PIN(24),
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JAGUAR2_PIN(25),
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JAGUAR2_PIN(26),
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JAGUAR2_PIN(27),
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JAGUAR2_PIN(28),
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JAGUAR2_PIN(29),
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JAGUAR2_PIN(30),
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JAGUAR2_PIN(31),
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JAGUAR2_PIN(32),
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JAGUAR2_PIN(33),
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JAGUAR2_PIN(34),
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JAGUAR2_PIN(35),
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JAGUAR2_PIN(36),
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JAGUAR2_PIN(37),
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JAGUAR2_PIN(38),
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JAGUAR2_PIN(39),
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JAGUAR2_PIN(40),
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JAGUAR2_PIN(41),
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JAGUAR2_PIN(42),
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JAGUAR2_PIN(43),
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JAGUAR2_PIN(44),
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JAGUAR2_PIN(45),
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JAGUAR2_PIN(46),
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JAGUAR2_PIN(47),
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JAGUAR2_PIN(48),
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JAGUAR2_PIN(49),
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JAGUAR2_PIN(50),
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JAGUAR2_PIN(51),
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JAGUAR2_PIN(52),
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JAGUAR2_PIN(53),
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JAGUAR2_PIN(54),
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JAGUAR2_PIN(55),
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JAGUAR2_PIN(56),
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JAGUAR2_PIN(57),
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JAGUAR2_PIN(58),
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JAGUAR2_PIN(59),
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JAGUAR2_PIN(60),
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JAGUAR2_PIN(61),
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JAGUAR2_PIN(62),
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JAGUAR2_PIN(63),
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};
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static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(ocelot_function_names);
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@ -207,9 +382,10 @@ static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
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return 0;
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}
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static int ocelot_pin_function_idx(unsigned int pin, unsigned int function)
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static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
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unsigned int pin, unsigned int function)
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{
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struct ocelot_pin_caps *p = ocelot_pins[pin].drv_data;
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struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
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int i;
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for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
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@ -220,14 +396,17 @@ static int ocelot_pin_function_idx(unsigned int pin, unsigned int function)
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return -1;
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}
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#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
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static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int selector, unsigned int group)
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{
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct ocelot_pin_caps *pin = ocelot_pins[group].drv_data;
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struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
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unsigned int p = pin->pin % 32;
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int f;
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f = ocelot_pin_function_idx(group, selector);
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f = ocelot_pin_function_idx(info, group, selector);
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if (f < 0)
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return -EINVAL;
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@ -238,10 +417,10 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
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* This is racy because both registers can't be updated at the same time
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* but it doesn't matter much for now.
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*/
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regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(pin->pin),
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f << pin->pin);
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regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(pin->pin),
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f << (pin->pin - 1));
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regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, pin->pin),
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BIT(p), f << p);
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regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, pin->pin),
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BIT(p), f << (p - 1));
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return 0;
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}
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@ -251,9 +430,10 @@ static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
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unsigned int pin, bool input)
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{
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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unsigned int p = pin % 32;
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regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin),
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input ? 0 : BIT(pin));
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regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, p), BIT(p),
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input ? 0 : BIT(p));
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return 0;
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}
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@ -263,9 +443,12 @@ static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
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unsigned int offset)
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{
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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unsigned int p = offset % 32;
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regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(offset), 0);
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regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(offset), 0);
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regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, offset),
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BIT(p), 0);
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regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, offset),
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BIT(p), 0);
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return 0;
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}
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@ -281,13 +464,17 @@ static const struct pinmux_ops ocelot_pmx_ops = {
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static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(ocelot_pins);
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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return info->desc->npins;
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}
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static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group)
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{
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return ocelot_pins[group].name;
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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return info->desc->pins[group].name;
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}
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static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
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@ -295,7 +482,9 @@ static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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*pins = &ocelot_pins[group].number;
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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*pins = &info->desc->pins[group].number;
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*num_pins = 1;
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return 0;
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@ -318,30 +507,47 @@ static struct pinctrl_desc ocelot_desc = {
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.owner = THIS_MODULE,
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};
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static struct pinctrl_desc jaguar2_desc = {
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.name = "jaguar2-pinctrl",
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.pins = jaguar2_pins,
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.npins = ARRAY_SIZE(jaguar2_pins),
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.pctlops = &ocelot_pctl_ops,
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.pmxops = &ocelot_pmx_ops,
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.owner = THIS_MODULE,
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};
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static int ocelot_create_group_func_map(struct device *dev,
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struct ocelot_pinctrl *info)
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{
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u16 pins[ARRAY_SIZE(ocelot_pins)];
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int f, npins, i;
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u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
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if (!pins)
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return -ENOMEM;
|
||||
|
||||
for (f = 0; f < FUNC_MAX; f++) {
|
||||
for (npins = 0, i = 0; i < ARRAY_SIZE(ocelot_pins); i++) {
|
||||
if (ocelot_pin_function_idx(i, f) >= 0)
|
||||
for (npins = 0, i = 0; i < info->desc->npins; i++) {
|
||||
if (ocelot_pin_function_idx(info, i, f) >= 0)
|
||||
pins[npins++] = i;
|
||||
}
|
||||
|
||||
if (!npins)
|
||||
continue;
|
||||
|
||||
info->func[f].ngroups = npins;
|
||||
info->func[f].groups = devm_kcalloc(dev,
|
||||
npins,
|
||||
sizeof(char *),
|
||||
GFP_KERNEL);
|
||||
if (!info->func[f].groups)
|
||||
info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
|
||||
GFP_KERNEL);
|
||||
if (!info->func[f].groups) {
|
||||
kfree(pins);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
for (i = 0; i < npins; i++)
|
||||
info->func[f].groups[i] = ocelot_pins[pins[i]].name;
|
||||
info->func[f].groups[i] = info->desc->pins[pins[i]].name;
|
||||
}
|
||||
|
||||
kfree(pins);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -356,7 +562,7 @@ static int ocelot_pinctrl_register(struct platform_device *pdev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
info->pctl = devm_pinctrl_register(&pdev->dev, &ocelot_desc, info);
|
||||
info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
|
||||
if (IS_ERR(info->pctl)) {
|
||||
dev_err(&pdev->dev, "Failed to register pinctrl\n");
|
||||
return PTR_ERR(info->pctl);
|
||||
|
@ -370,9 +576,9 @@ static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
|||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int val;
|
||||
|
||||
regmap_read(info->map, OCELOT_GPIO_IN, &val);
|
||||
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
|
||||
|
||||
return !!(val & BIT(offset));
|
||||
return !!(val & BIT(offset % 32));
|
||||
}
|
||||
|
||||
static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
|
@ -381,9 +587,11 @@ static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
|||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
|
||||
if (value)
|
||||
regmap_write(info->map, OCELOT_GPIO_OUT_SET, BIT(offset));
|
||||
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
|
||||
BIT(offset % 32));
|
||||
else
|
||||
regmap_write(info->map, OCELOT_GPIO_OUT_CLR, BIT(offset));
|
||||
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
|
||||
BIT(offset % 32));
|
||||
}
|
||||
|
||||
static int ocelot_gpio_get_direction(struct gpio_chip *chip,
|
||||
|
@ -392,9 +600,9 @@ static int ocelot_gpio_get_direction(struct gpio_chip *chip,
|
|||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int val;
|
||||
|
||||
regmap_read(info->map, OCELOT_GPIO_OE, &val);
|
||||
regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
|
||||
|
||||
return !(val & BIT(offset));
|
||||
return !(val & BIT(offset % 32));
|
||||
}
|
||||
|
||||
static int ocelot_gpio_direction_input(struct gpio_chip *chip,
|
||||
|
@ -407,12 +615,14 @@ static int ocelot_gpio_direction_output(struct gpio_chip *chip,
|
|||
unsigned int offset, int value)
|
||||
{
|
||||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int pin = BIT(offset);
|
||||
unsigned int pin = BIT(offset % 32);
|
||||
|
||||
if (value)
|
||||
regmap_write(info->map, OCELOT_GPIO_OUT_SET, pin);
|
||||
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
|
||||
pin);
|
||||
else
|
||||
regmap_write(info->map, OCELOT_GPIO_OUT_CLR, pin);
|
||||
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
|
||||
pin);
|
||||
|
||||
return pinctrl_gpio_direction_output(chip->base + offset);
|
||||
}
|
||||
|
@ -434,7 +644,8 @@ static void ocelot_irq_mask(struct irq_data *data)
|
|||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int gpio = irqd_to_hwirq(data);
|
||||
|
||||
regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio), 0);
|
||||
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
|
||||
BIT(gpio % 32), 0);
|
||||
}
|
||||
|
||||
static void ocelot_irq_unmask(struct irq_data *data)
|
||||
|
@ -443,8 +654,8 @@ static void ocelot_irq_unmask(struct irq_data *data)
|
|||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int gpio = irqd_to_hwirq(data);
|
||||
|
||||
regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio),
|
||||
BIT(gpio));
|
||||
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
|
||||
BIT(gpio % 32), BIT(gpio % 32));
|
||||
}
|
||||
|
||||
static void ocelot_irq_ack(struct irq_data *data)
|
||||
|
@ -453,7 +664,8 @@ static void ocelot_irq_ack(struct irq_data *data)
|
|||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int gpio = irqd_to_hwirq(data);
|
||||
|
||||
regmap_write_bits(info->map, OCELOT_GPIO_INTR, BIT(gpio), BIT(gpio));
|
||||
regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
|
||||
BIT(gpio % 32), BIT(gpio % 32));
|
||||
}
|
||||
|
||||
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
|
||||
|
@ -497,22 +709,25 @@ static void ocelot_irq_handler(struct irq_desc *desc)
|
|||
struct irq_chip *parent_chip = irq_desc_get_chip(desc);
|
||||
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
|
||||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int reg = 0, irq;
|
||||
unsigned int reg = 0, irq, i;
|
||||
unsigned long irqs;
|
||||
|
||||
regmap_read(info->map, OCELOT_GPIO_INTR_IDENT, ®);
|
||||
if (!reg)
|
||||
return;
|
||||
for (i = 0; i < info->stride; i++) {
|
||||
regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, ®);
|
||||
if (!reg)
|
||||
continue;
|
||||
|
||||
chained_irq_enter(parent_chip, desc);
|
||||
chained_irq_enter(parent_chip, desc);
|
||||
|
||||
irqs = reg;
|
||||
irqs = reg;
|
||||
|
||||
for_each_set_bit(irq, &irqs, OCELOT_PINS) {
|
||||
generic_handle_irq(irq_linear_revmap(chip->irq.domain, irq));
|
||||
for_each_set_bit(irq, &irqs,
|
||||
min(32U, info->desc->npins - 32 * i))
|
||||
generic_handle_irq(irq_linear_revmap(chip->irq.domain,
|
||||
irq + 32 * i));
|
||||
|
||||
chained_irq_exit(parent_chip, desc);
|
||||
}
|
||||
|
||||
chained_irq_exit(parent_chip, desc);
|
||||
}
|
||||
|
||||
static int ocelot_gpiochip_register(struct platform_device *pdev,
|
||||
|
@ -524,7 +739,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
|
|||
info->gpio_chip = ocelot_gpiolib_chip;
|
||||
|
||||
gc = &info->gpio_chip;
|
||||
gc->ngpio = OCELOT_PINS;
|
||||
gc->ngpio = info->desc->npins;
|
||||
gc->parent = &pdev->dev;
|
||||
gc->base = 0;
|
||||
gc->of_node = info->dev->of_node;
|
||||
|
@ -549,15 +764,9 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct regmap_config ocelot_pinctrl_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = 0x64,
|
||||
};
|
||||
|
||||
static const struct of_device_id ocelot_pinctrl_of_match[] = {
|
||||
{ .compatible = "mscc,ocelot-pinctrl" },
|
||||
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
|
||||
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
|
||||
{},
|
||||
};
|
||||
|
||||
|
@ -567,11 +776,18 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
|
|||
struct ocelot_pinctrl *info;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
struct regmap_config regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
|
||||
info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
|
||||
|
||||
base = devm_ioremap_resource(dev,
|
||||
platform_get_resource(pdev, IORESOURCE_MEM, 0));
|
||||
if (IS_ERR(base)) {
|
||||
|
@ -579,8 +795,10 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(base);
|
||||
}
|
||||
|
||||
info->map = devm_regmap_init_mmio(dev, base,
|
||||
&ocelot_pinctrl_regmap_config);
|
||||
info->stride = 1 + (info->desc->npins - 1) / 32;
|
||||
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
|
||||
|
||||
info->map = devm_regmap_init_mmio(dev, base, ®map_config);
|
||||
if (IS_ERR(info->map)) {
|
||||
dev_err(dev, "Failed to create regmap\n");
|
||||
return PTR_ERR(info->map);
|
||||
|
|
Loading…
Reference in a new issue