[PATCH] tpm: Support new National TPMs
This patch is work to support new National TPMs that problems were reported with on Thinkpad T43 and Thinkcentre S51. Thanks to Jens and Gang for their debugging work on these issues. Signed-off-by: Kylene Hall <kjhall@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -31,8 +31,8 @@ enum tpm_timeout {
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/* TPM addresses */
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enum tpm_addr {
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TPM_SUPERIO_ADDR = 0x2E,
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TPM_ADDR = 0x4E,
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TPM_DATA = 0x4F
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};
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extern ssize_t tpm_show_pubek(struct device *, struct device_attribute *attr,
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@ -79,16 +79,16 @@ struct tpm_chip {
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struct list_head list;
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};
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static inline int tpm_read_index(int index)
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static inline int tpm_read_index(int base, int index)
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{
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outb(index, TPM_ADDR);
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return inb(TPM_DATA) & 0xFF;
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outb(index, base);
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return inb(base+1) & 0xFF;
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}
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static inline void tpm_write_index(int index, int value)
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static inline void tpm_write_index(int base, int index, int value)
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{
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outb(index, TPM_ADDR);
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outb(value & 0xFF, TPM_DATA);
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outb(index, base);
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outb(value & 0xFF, base+1);
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}
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extern int tpm_register_hardware(struct pci_dev *,
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@ -163,24 +163,24 @@ static int __devinit tpm_atml_init(struct pci_dev *pci_dev,
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if (pci_enable_device(pci_dev))
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return -EIO;
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lo = tpm_read_index( TPM_ATMEL_BASE_ADDR_LO );
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hi = tpm_read_index( TPM_ATMEL_BASE_ADDR_HI );
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lo = tpm_read_index(TPM_ADDR, TPM_ATMEL_BASE_ADDR_LO);
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hi = tpm_read_index(TPM_ADDR, TPM_ATMEL_BASE_ADDR_HI);
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tpm_atmel.base = (hi<<8)|lo;
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dev_dbg( &pci_dev->dev, "Operating with base: 0x%x\n", tpm_atmel.base);
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/* verify that it is an Atmel part */
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if (tpm_read_index(4) != 'A' || tpm_read_index(5) != 'T'
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|| tpm_read_index(6) != 'M' || tpm_read_index(7) != 'L') {
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if (tpm_read_index(TPM_ADDR, 4) != 'A' || tpm_read_index(TPM_ADDR, 5) != 'T'
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|| tpm_read_index(TPM_ADDR, 6) != 'M' || tpm_read_index(TPM_ADDR, 7) != 'L') {
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rc = -ENODEV;
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goto out_err;
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}
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/* query chip for its version number */
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if ((version[0] = tpm_read_index(0x00)) != 0xFF) {
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version[1] = tpm_read_index(0x01);
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version[2] = tpm_read_index(0x02);
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version[3] = tpm_read_index(0x03);
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if ((version[0] = tpm_read_index(TPM_ADDR, 0x00)) != 0xFF) {
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version[1] = tpm_read_index(TPM_ADDR, 0x01);
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version[2] = tpm_read_index(TPM_ADDR, 0x02);
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version[3] = tpm_read_index(TPM_ADDR, 0x03);
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} else {
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dev_info(&pci_dev->dev, "version query failed\n");
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rc = -ENODEV;
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@ -23,7 +23,6 @@
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/* National definitions */
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enum tpm_nsc_addr{
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TPM_NSC_BASE = 0x360,
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TPM_NSC_IRQ = 0x07,
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TPM_NSC_BASE0_HI = 0x60,
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TPM_NSC_BASE0_LO = 0x61,
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@ -56,6 +55,7 @@ enum tpm_nsc_status {
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NSC_STATUS_RDY = 0x10, /* ready to receive command */
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NSC_STATUS_IBR = 0x20 /* ready to receive data */
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};
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/* command bits */
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enum tpm_nsc_cmd_mode {
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NSC_COMMAND_NORMAL = 0x01, /* normal mode */
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@ -150,7 +150,8 @@ static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
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*p = inb(chip->vendor->base + NSC_DATA);
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}
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if ((data & NSC_STATUS_F0) == 0) {
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if ((data & NSC_STATUS_F0) == 0 &&
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(wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
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dev_err(&chip->pci_dev->dev, "F0 not set\n");
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return -EIO;
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}
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@ -259,85 +260,64 @@ static int __devinit tpm_nsc_init(struct pci_dev *pci_dev,
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{
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int rc = 0;
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int lo, hi;
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int nscAddrBase = TPM_ADDR;
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hi = tpm_read_index(TPM_NSC_BASE0_HI);
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lo = tpm_read_index(TPM_NSC_BASE0_LO);
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tpm_nsc.base = (hi<<8) | lo;
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if (pci_enable_device(pci_dev))
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return -EIO;
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/* select PM channel 1 */
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tpm_write_index(nscAddrBase,NSC_LDN_INDEX, 0x12);
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/* verify that it is a National part (SID) */
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if (tpm_read_index(NSC_SID_INDEX) != 0xEF) {
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rc = -ENODEV;
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goto out_err;
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if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
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nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
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(tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
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if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6) {
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rc = -ENODEV;
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goto out_err;
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}
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}
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hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
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lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
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tpm_nsc.base = (hi<<8) | lo;
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dev_dbg(&pci_dev->dev, "NSC TPM detected\n");
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dev_dbg(&pci_dev->dev,
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"NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
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tpm_read_index(0x07), tpm_read_index(0x20),
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tpm_read_index(0x27));
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tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
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tpm_read_index(nscAddrBase,0x27));
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dev_dbg(&pci_dev->dev,
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"NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
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tpm_read_index(0x21), tpm_read_index(0x25),
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tpm_read_index(0x26), tpm_read_index(0x28));
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tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
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tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
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dev_dbg(&pci_dev->dev, "NSC IO Base0 0x%x\n",
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(tpm_read_index(0x60) << 8) | tpm_read_index(0x61));
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(tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
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dev_dbg(&pci_dev->dev, "NSC IO Base1 0x%x\n",
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(tpm_read_index(0x62) << 8) | tpm_read_index(0x63));
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(tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
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dev_dbg(&pci_dev->dev, "NSC Interrupt number and wakeup 0x%x\n",
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tpm_read_index(0x70));
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tpm_read_index(nscAddrBase,0x70));
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dev_dbg(&pci_dev->dev, "NSC IRQ type select 0x%x\n",
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tpm_read_index(0x71));
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tpm_read_index(nscAddrBase,0x71));
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dev_dbg(&pci_dev->dev,
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"NSC DMA channel select0 0x%x, select1 0x%x\n",
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tpm_read_index(0x74), tpm_read_index(0x75));
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tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
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dev_dbg(&pci_dev->dev,
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"NSC Config "
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"0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
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tpm_read_index(0xF0), tpm_read_index(0xF1),
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tpm_read_index(0xF2), tpm_read_index(0xF3),
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tpm_read_index(0xF4), tpm_read_index(0xF5),
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tpm_read_index(0xF6), tpm_read_index(0xF7),
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tpm_read_index(0xF8), tpm_read_index(0xF9));
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tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
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tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
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tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
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tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
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tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
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dev_info(&pci_dev->dev,
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"NSC PC21100 TPM revision %d\n",
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tpm_read_index(0x27) & 0x1F);
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if (tpm_read_index(NSC_LDC_INDEX) == 0)
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dev_info(&pci_dev->dev, ": NSC TPM not active\n");
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/* select PM channel 1 */
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tpm_write_index(NSC_LDN_INDEX, 0x12);
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tpm_read_index(NSC_LDN_INDEX);
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/* disable the DPM module */
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tpm_write_index(NSC_LDC_INDEX, 0);
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tpm_read_index(NSC_LDC_INDEX);
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/* set the data register base addresses */
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tpm_write_index(NSC_DIO_INDEX, TPM_NSC_BASE >> 8);
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tpm_write_index(NSC_DIO_INDEX + 1, TPM_NSC_BASE);
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tpm_read_index(NSC_DIO_INDEX);
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tpm_read_index(NSC_DIO_INDEX + 1);
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/* set the command register base addresses */
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tpm_write_index(NSC_CIO_INDEX, (TPM_NSC_BASE + 1) >> 8);
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tpm_write_index(NSC_CIO_INDEX + 1, (TPM_NSC_BASE + 1));
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tpm_read_index(NSC_DIO_INDEX);
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tpm_read_index(NSC_DIO_INDEX + 1);
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/* set the interrupt number to be used for the host interface */
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tpm_write_index(NSC_IRQ_INDEX, TPM_NSC_IRQ);
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tpm_write_index(NSC_ITS_INDEX, 0x00);
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tpm_read_index(NSC_IRQ_INDEX);
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"NSC TPM revision %d\n",
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tpm_read_index(nscAddrBase, 0x27) & 0x1F);
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/* enable the DPM module */
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tpm_write_index(NSC_LDC_INDEX, 0x01);
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tpm_read_index(NSC_LDC_INDEX);
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tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
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if ((rc = tpm_register_hardware(pci_dev, &tpm_nsc)) < 0)
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goto out_err;
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@ -355,6 +335,9 @@ static struct pci_device_id tpm_pci_tbl[] __devinitdata = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0)},
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{PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_LPC)},
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{0,}
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};
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