ASoC: dwc: Iterate over all channels
The Designware core can be configured with up to four stereo channels. Each stereo channel is individually configured so, when the driver's hw_params call is made, each requested stereo channel has to be programmed. Signed-off-by: Andrew Jackson <Andrew.Jackson@arm.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -209,16 +209,9 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
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switch (config->chan_nr) {
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case EIGHT_CHANNEL_SUPPORT:
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ch_reg = 3;
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break;
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case SIX_CHANNEL_SUPPORT:
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ch_reg = 2;
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break;
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case FOUR_CHANNEL_SUPPORT:
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ch_reg = 1;
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break;
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case TWO_CHANNEL_SUPPORT:
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ch_reg = 0;
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break;
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default:
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dev_err(dev->dev, "channel not supported\n");
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@ -227,18 +220,22 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
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i2s_disable_channels(dev, substream->stream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution);
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i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
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irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
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i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
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i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
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} else {
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i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution);
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i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
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irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
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i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
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i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
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for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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i2s_write_reg(dev->i2s_base, TCR(ch_reg),
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xfer_resolution);
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i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
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irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
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i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
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i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
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} else {
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i2s_write_reg(dev->i2s_base, RCR(ch_reg),
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xfer_resolution);
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i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
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irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
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i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
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i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
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}
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}
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i2s_write_reg(dev->i2s_base, CCR, ccr);
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