ARM: dts: dra7: Fix clock data for gmac_gmii_ref_clk_div
This commit fixes the clock data inside the DRA7xx clocks device tree structure for the gmac_gmii_ref_clk_div clock. This clock is actually the GMAC_MAIN_CLK and has nothing to do with the register at address 0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is set to 1 in order to use the GMAC_RMII_CLK instead of the GMAC_RMII_HS_CLK, the kernel generates a clock divider warning: WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0() gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to have the parent of dpll_gmac_m2_ck always divided by 2 the warning is resolved and the clock tree is fixed up. Additionally, a new clock called rmii_50mhz_clk_mux is defined that does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the source clock for the RMII_50MHZ_CLK. Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: J.D. Schroeder <jay.schroeder@garmin.com> Reviewed-by: Trenton Andres <trenton.andres@garmin.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -1718,13 +1718,20 @@
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reg = <0x0c00>;
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};
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gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 {
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rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_gmac_m2_ck>;
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compatible = "ti,mux-clock";
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clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
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ti,bit-shift = <24>;
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reg = <0x13d0>;
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ti,dividers = <2>;
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};
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gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_gmac_m2_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
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