atmel_spi: fix hang due to missed interrupt
For some time my at91sam9260 board with JFFS2 on serial flash (m25p80) would hang when accessing the serial flash and SPI bus. Slowing the SPI clock down to 9 MHz reduced the occurrence of the hang from "always" during boot to a nuisance level that allowed other SW development to continue. Finally had to address this issue when an application stresses the I/O to always cause a hang. Hang seems to be caused by a missed SPI interrupt, so that the task ends up waiting forever after calling spi_sync(). The fix has 2 parts. First is to halt the DMA engine before the "current" PDC registers are loaded. This ensures that the "next" registers are loaded before the DMA operation takes off. The second part of the fix is a kludge that adds a "completion" interrupt in case the ENDRX interrupt for the last segment of the DMA chaining operation was missed. The patch allows the SPI clock for the serial flash to be increased from 9 MHz to 15 MHz (or more?). No hangs or SPI overruns were encountered. Haavard: while this patch does indeed improve things, I still see overruns and CRC errors on my NGW100 board when running the DataFlash at 10 MHz. However, I think some improvement is better than nothing, so I'm passing this on for inclusion in 2.6.27. Signed-off-by: Gerard Kam <gerardk5@verizon.net> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -184,7 +184,8 @@ static void atmel_spi_next_xfer(struct spi_master *master,
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{
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_transfer *xfer;
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u32 len, remaining, total;
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u32 len, remaining;
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u32 ieval;
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dma_addr_t tx_dma, rx_dma;
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if (!as->current_transfer)
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@ -197,6 +198,8 @@ static void atmel_spi_next_xfer(struct spi_master *master,
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xfer = NULL;
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if (xfer) {
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spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
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len = xfer->len;
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atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
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remaining = xfer->len - len;
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@ -234,6 +237,8 @@ static void atmel_spi_next_xfer(struct spi_master *master,
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as->next_transfer = xfer;
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if (xfer) {
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u32 total;
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total = len;
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atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
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as->next_remaining_bytes = total - len;
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@ -250,9 +255,11 @@ static void atmel_spi_next_xfer(struct spi_master *master,
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" next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
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xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
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xfer->rx_buf, xfer->rx_dma);
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ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
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} else {
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spi_writel(as, RNCR, 0);
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spi_writel(as, TNCR, 0);
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ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
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}
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/* REVISIT: We're waiting for ENDRX before we start the next
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@ -265,7 +272,7 @@ static void atmel_spi_next_xfer(struct spi_master *master,
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*
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* It should be doable, though. Just not now...
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*/
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spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
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spi_writel(as, IER, ieval);
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spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
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}
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@ -396,7 +403,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
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ret = IRQ_HANDLED;
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spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX)
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spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
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| SPI_BIT(OVRES)));
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/*
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@ -418,7 +425,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
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if (xfer->delay_usecs)
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udelay(xfer->delay_usecs);
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dev_warn(master->dev.parent, "fifo overrun (%u/%u remaining)\n",
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dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
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spi_readl(as, TCR), spi_readl(as, RCR));
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/*
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@ -442,7 +449,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
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spi_readl(as, SR);
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atmel_spi_msg_done(master, as, msg, -EIO, 0);
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} else if (pending & SPI_BIT(ENDRX)) {
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} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
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ret = IRQ_HANDLED;
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spi_writel(as, IDR, pending);
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