drm/radeon: set correct CE ram size for CIK
CE ram size is 32k/0k/0k for GFX/CS0/CS1 with CIK Ported from amdgpu driver. Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev)
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/* init the CE partitions. CE only used for gfx on CIK */
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radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
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radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
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radeon_ring_write(ring, 0xc000);
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radeon_ring_write(ring, 0xc000);
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radeon_ring_write(ring, 0x8000);
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radeon_ring_write(ring, 0x8000);
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/* setup clear context state */
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radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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