MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control
Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits are a more suitable layout. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
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@ -252,14 +252,6 @@ asm(" .am33_2\n");
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#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */
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#define xPTEL_PPN 0xfffff006 /* physical page number */
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#define xPTEL_V_BIT 0 /* bit numbers corresponding to above masks */
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#define xPTEL_UNUSED1_BIT 1
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#define xPTEL_UNUSED2_BIT 2
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#define xPTEL_C_BIT 3
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#define xPTEL_PV_BIT 4
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#define xPTEL_D_BIT 5
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#define xPTEL_G_BIT 9
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#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
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#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
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#define xPTEU_VPN 0xfffffc00 /* virtual page number */
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@ -283,7 +275,16 @@ asm(" .am33_2\n");
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#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */
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#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */
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#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */
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#define xPTEL2_PPN 0xfffffc00 /* physical page number */
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#define xPTEL2_CWT 0x00000400 /* cacheable write-through */
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#define xPTEL2_UNUSED1 0x00000800 /* unused bit (broadcast mask) */
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#define xPTEL2_PPN 0xfffff000 /* physical page number */
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#define xPTEL2_V_BIT 0 /* bit numbers corresponding to above masks */
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#define xPTEL2_C_BIT 1
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#define xPTEL2_PV_BIT 2
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#define xPTEL2_D_BIT 3
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#define xPTEL2_G_BIT 7
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#define xPTEL2_UNUSED1_BIT 11
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#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */
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#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */
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@ -98,38 +98,44 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE];
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#endif
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/* IPTEL/DPTEL bit assignments */
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#define _PAGE_BIT_VALID xPTEL_V_BIT
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#define _PAGE_BIT_ACCESSED xPTEL_UNUSED1_BIT /* mustn't be loaded into IPTEL/DPTEL */
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#define _PAGE_BIT_NX xPTEL_UNUSED2_BIT /* mustn't be loaded into IPTEL/DPTEL */
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#define _PAGE_BIT_CACHE xPTEL_C_BIT
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#define _PAGE_BIT_PRESENT xPTEL_PV_BIT
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#define _PAGE_BIT_DIRTY xPTEL_D_BIT
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#define _PAGE_BIT_GLOBAL xPTEL_G_BIT
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/* IPTEL2/DPTEL2 bit assignments */
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#define _PAGE_BIT_VALID xPTEL2_V_BIT
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#define _PAGE_BIT_CACHE xPTEL2_C_BIT
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#define _PAGE_BIT_PRESENT xPTEL2_PV_BIT
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#define _PAGE_BIT_DIRTY xPTEL2_D_BIT
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#define _PAGE_BIT_GLOBAL xPTEL2_G_BIT
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#define _PAGE_BIT_ACCESSED xPTEL2_UNUSED1_BIT /* mustn't be loaded into IPTEL2/DPTEL2 */
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#define _PAGE_VALID xPTEL_V
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#define _PAGE_ACCESSED xPTEL_UNUSED1
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#define _PAGE_NX xPTEL_UNUSED2 /* no-execute bit */
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#define _PAGE_CACHE xPTEL_C
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#define _PAGE_PRESENT xPTEL_PV
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#define _PAGE_DIRTY xPTEL_D
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#define _PAGE_PROT xPTEL_PR
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#define _PAGE_PROT_RKNU xPTEL_PR_ROK
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#define _PAGE_PROT_WKNU xPTEL_PR_RWK
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#define _PAGE_PROT_RKRU xPTEL_PR_ROK_ROU
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#define _PAGE_PROT_WKRU xPTEL_PR_RWK_ROU
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#define _PAGE_PROT_WKWU xPTEL_PR_RWK_RWU
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#define _PAGE_GLOBAL xPTEL_G
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#define _PAGE_PSE xPTEL_PS_4Mb /* 4MB page */
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#define _PAGE_VALID xPTEL2_V
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#define _PAGE_CACHE xPTEL2_C
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#define _PAGE_PRESENT xPTEL2_PV
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#define _PAGE_DIRTY xPTEL2_D
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#define _PAGE_PROT xPTEL2_PR
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#define _PAGE_PROT_RKNU xPTEL2_PR_ROK
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#define _PAGE_PROT_WKNU xPTEL2_PR_RWK
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#define _PAGE_PROT_RKRU xPTEL2_PR_ROK_ROU
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#define _PAGE_PROT_WKRU xPTEL2_PR_RWK_ROU
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#define _PAGE_PROT_WKWU xPTEL2_PR_RWK_RWU
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#define _PAGE_GLOBAL xPTEL2_G
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#define _PAGE_PS_MASK xPTEL2_PS
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#define _PAGE_PS_4Kb xPTEL2_PS_4Kb
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#define _PAGE_PS_128Kb xPTEL2_PS_128Kb
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#define _PAGE_PS_1Kb xPTEL2_PS_1Kb
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#define _PAGE_PS_4Mb xPTEL2_PS_4Mb
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#define _PAGE_PSE xPTEL2_PS_4Mb /* 4MB page */
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#define _PAGE_CACHE_WT xPTEL2_CWT
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#define _PAGE_ACCESSED xPTEL2_UNUSED1
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#define _PAGE_NX 0 /* no-execute bit */
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#define _PAGE_FILE xPTEL_UNUSED1_BIT /* set:pagecache unset:swap */
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/* If _PAGE_VALID is clear, we use these: */
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#define _PAGE_FILE xPTEL2_C /* set:pagecache unset:swap */
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#define _PAGE_PROTNONE 0x000 /* If not present */
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#define __PAGE_PROT_UWAUX 0x040
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#define __PAGE_PROT_USER 0x080
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#define __PAGE_PROT_WRITE 0x100
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#define __PAGE_PROT_UWAUX 0x010
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#define __PAGE_PROT_USER 0x020
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#define __PAGE_PROT_WRITE 0x040
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#define _PAGE_PRESENTV (_PAGE_PRESENT|_PAGE_VALID)
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#define _PAGE_PROTNONE 0x000 /* If not present */
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#ifndef __ASSEMBLY__
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@ -61,10 +61,16 @@ ENTRY(itlb_miss)
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btst _PAGE_VALID,d2
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beq itlb_miss_fault # jump if doesn't point to a page
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# (might be a swap id)
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#if ((_PAGE_ACCESSED & 0xffffff00) == 0)
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bset _PAGE_ACCESSED,(0,a2)
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and ~(xPTEL_UNUSED1|xPTEL_UNUSED2),d2
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#elif ((_PAGE_ACCESSED & 0xffff00ff) == 0)
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bset +(_PAGE_ACCESSED >> 8),(1,a2)
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#else
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#error "_PAGE_ACCESSED value is out of range"
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#endif
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and ~xPTEL2_UNUSED1,d2
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itlb_miss_set:
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mov d2,(IPTEL) # change the TLB
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mov d2,(IPTEL2) # change the TLB
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#ifdef CONFIG_GDBSTUB
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movm (sp),[d2,d3,a2]
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#endif
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@ -118,10 +124,16 @@ ENTRY(dtlb_miss)
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btst _PAGE_VALID,d2
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beq dtlb_miss_fault # jump if doesn't point to a page
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# (might be a swap id)
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#if ((_PAGE_ACCESSED & 0xffffff00) == 0)
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bset _PAGE_ACCESSED,(0,a2)
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and ~(xPTEL_UNUSED1|xPTEL_UNUSED2),d2
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#elif ((_PAGE_ACCESSED & 0xffff00ff) == 0)
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bset +(_PAGE_ACCESSED >> 8),(1,a2)
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#else
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#error "_PAGE_ACCESSED value is out of range"
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#endif
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and ~xPTEL2_UNUSED1,d2
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dtlb_miss_set:
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mov d2,(DPTEL) # change the TLB
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mov d2,(DPTEL2) # change the TLB
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#ifdef CONFIG_GDBSTUB
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movm (sp),[d2,d3,a2]
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#endif
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@ -156,13 +168,12 @@ ENTRY(itlb_aerror)
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or 0x00010000,d1 # it's an instruction fetch
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# determine the page address
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mov (IPTEU),a2
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mov a2,d0
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mov (IPTEU),d0
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and PAGE_MASK,d0
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mov d0,(12,sp)
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clr d0
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mov d0,(IPTEL)
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mov d0,(IPTEL2)
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or EPSW_IE,epsw
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mov fp,d0
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@ -199,7 +210,7 @@ ENTRY(dtlb_aerror)
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mov d0,(12,sp)
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clr d0
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mov d0,(DPTEL)
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mov d0,(DPTEL2)
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or EPSW_IE,epsw
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mov fp,d0
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