iommu/arm-smmu-v3: Support 52-bit virtual address
Stage 1 input addresses are effectively 64-bit in SMMUv3 anyway, so really all that's involved is letting io-pgtable know the appropriate upper bound for T0SZ. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -92,6 +92,8 @@
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#define IDR5_OAS_44_BIT 4
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#define IDR5_OAS_48_BIT 5
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#define IDR5_OAS_52_BIT 6
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#define IDR5_VAX GENMASK(11, 10)
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#define IDR5_VAX_52_BIT 1
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#define ARM_SMMU_CR0 0x20
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#define CR0_CMDQEN (1 << 3)
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@ -551,6 +553,7 @@ struct arm_smmu_device {
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#define ARM_SMMU_FEAT_STALLS (1 << 11)
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#define ARM_SMMU_FEAT_HYP (1 << 12)
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#define ARM_SMMU_FEAT_STALL_FORCE (1 << 13)
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#define ARM_SMMU_FEAT_VAX (1 << 14)
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u32 features;
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#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
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@ -1591,7 +1594,8 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)
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switch (smmu_domain->stage) {
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case ARM_SMMU_DOMAIN_S1:
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ias = VA_BITS;
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ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48;
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ias = min_t(unsigned long, ias, VA_BITS);
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oas = smmu->ias;
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fmt = ARM_64_LPAE_S1;
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finalise_stage_fn = arm_smmu_domain_finalise_s1;
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@ -2645,6 +2649,10 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
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if (reg & IDR5_GRAN4K)
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smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
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/* Input address size */
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if (FIELD_GET(IDR5_VAX, reg) == IDR5_VAX_52_BIT)
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smmu->features |= ARM_SMMU_FEAT_VAX;
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/* Output address size */
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switch (FIELD_GET(IDR5_OAS, reg)) {
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case IDR5_OAS_32_BIT:
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