ARM: orion: switch to a per-platform handle_irq() function
Moving to the Device Tree implies having CONFIG_MULTI_IRQ_HANDLER enabled, even for non-DT platforms (if we want both DT and non-DT platforms to be supported in a single kernel). However, the common CONFIG_MULTI_IRQ_HANDLER handler for non-DT platforms in plat-orion/irq.c doesn't match the needs of Orion5x. Also, it doesn't make much sense for orion_irq_init() to register the multi-IRQ handler: orion_irq_init() is called once for each IRQ cause/mask tuple, while the multi-IRQ handler only needs to be registered once. To solve this problem, we move the multi-IRQ handle in per-platform code: mach-kirkwood/irq.c and mach-dove/irq.c. The Orion5x variant will be introduced in a followup commit. Of course, this code will ultimately be completely removed once all boards are converted to the Device Tree. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1398202002-28530-23-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -108,6 +108,38 @@ static int __initdata gpio2_irqs[4] = {
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0,
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};
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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/*
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* Compiling with both non-DT and DT support enabled, will
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* break asm irq handler used by non-DT boards. Therefore,
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* we provide a C-style irq handler even for non-DT boards,
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* if MULTI_IRQ_HANDLER is set.
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*/
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static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
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static asmlinkage void
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__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
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{
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u32 stat;
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stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
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stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
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if (stat) {
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unsigned int hwirq = __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
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stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
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if (stat) {
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unsigned int hwirq = 32 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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}
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#endif
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void __init dove_init_irq(void)
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{
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int i;
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@ -115,6 +147,10 @@ void __init dove_init_irq(void)
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orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
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orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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set_handle_irq(dove_legacy_handle_irq);
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#endif
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/*
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* Initialize gpiolib for GPIOs 0-71.
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*/
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@ -7,6 +7,7 @@
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/exception.h>
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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@ -30,11 +31,47 @@ static int __initdata gpio1_irqs[4] = {
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0,
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};
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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/*
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* Compiling with both non-DT and DT support enabled, will
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* break asm irq handler used by non-DT boards. Therefore,
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* we provide a C-style irq handler even for non-DT boards,
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* if MULTI_IRQ_HANDLER is set.
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*/
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static void __iomem *kirkwood_irq_base = IRQ_VIRT_BASE;
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asmlinkage void
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__exception_irq_entry kirkwood_legacy_handle_irq(struct pt_regs *regs)
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{
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u32 stat;
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stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_LOW_OFF);
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stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_LOW_OFF);
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if (stat) {
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unsigned int hwirq = __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_HIGH_OFF);
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stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_HIGH_OFF);
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if (stat) {
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unsigned int hwirq = 32 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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}
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#endif
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void __init kirkwood_init_irq(void)
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{
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orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
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orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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set_handle_irq(kirkwood_legacy_handle_irq);
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#endif
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/*
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* Initialize gpiolib for GPIOs 0-49.
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*/
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@ -20,47 +20,6 @@
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#include <plat/orion-gpio.h>
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#include <mach/bridge-regs.h>
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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/*
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* Compiling with both non-DT and DT support enabled, will
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* break asm irq handler used by non-DT boards. Therefore,
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* we provide a C-style irq handler even for non-DT boards,
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* if MULTI_IRQ_HANDLER is set.
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*
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* Notes:
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* - this is prepared for Kirkwood and Dove only, update
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* accordingly if you add Orion5x or MV78x00.
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* - Orion5x uses different macro names and has only one
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* set of CAUSE/MASK registers.
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* - MV78x00 uses the same macro names but has a third
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* set of CAUSE/MASK registers.
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*
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*/
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static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
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asmlinkage void
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__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
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{
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u32 stat;
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stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
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stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
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if (stat) {
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unsigned int hwirq = __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
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stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
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if (stat) {
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unsigned int hwirq = 32 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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}
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#endif
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void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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{
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struct irq_chip_generic *gc;
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@ -78,10 +37,6 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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set_handle_irq(orion_legacy_handle_irq);
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#endif
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}
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#ifdef CONFIG_OF
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