ARM: 6826/1: Merge v6 and v7 DEBUG_LL DCC support
The inline assembly differences for v6 vs. v7 are purely optimizations. On a v7 processor, an mrc with the pc sets the condition codes to the 28-31 bits of the register being read. It just so happens that the TX/RX full bits the DCC support code is testing for are high enough in the register to be put into the condition codes. On a v6 processor, this "feature" isn't implemented and thus we have to do the usual read, mask, test operations to check for TX/RX full. Thus, we can drop the v7 implementation and just use the v6 implementation for both. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -21,20 +21,12 @@
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#if defined(CONFIG_DEBUG_ICEDCC)
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
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.macro loadsp, rb, tmp
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.endm
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.macro writeb, ch, rb
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mcr p14, 0, \ch, c0, c5, 0
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.endm
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#elif defined(CONFIG_CPU_V7)
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.macro loadsp, rb, tmp
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.endm
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.macro writeb, ch, rb
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wait: mrc p14, 0, pc, c0, c1, 0
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bcs wait
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mcr p14, 0, \ch, c0, c5, 0
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.endm
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#elif defined(CONFIG_CPU_XSCALE)
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.macro loadsp, rb, tmp
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.endm
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@ -36,7 +36,7 @@ extern void error(char *x);
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#ifdef CONFIG_DEBUG_ICEDCC
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
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static void icedcc_putc(int ch)
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{
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@ -52,16 +52,6 @@ static void icedcc_putc(int ch)
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asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
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}
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#elif defined(CONFIG_CPU_V7)
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static void icedcc_putc(int ch)
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{
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asm(
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"wait: mrc p14, 0, pc, c0, c1, 0 \n\
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bcs wait \n\
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mcr p14, 0, %0, c0, c5, 0 "
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: : "r" (ch));
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}
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#elif defined(CONFIG_CPU_XSCALE)
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@ -25,7 +25,7 @@
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.macro addruart, rp, rv
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.endm
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
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.macro senduart, rd, rx
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mcr p14, 0, \rd, c0, c5, 0
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@ -49,23 +49,6 @@
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1002:
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.endm
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#elif defined(CONFIG_CPU_V7)
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.macro senduart, rd, rx
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mcr p14, 0, \rd, c0, c5, 0
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.endm
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.macro busyuart, rd, rx
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busy: mrc p14, 0, pc, c0, c1, 0
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bcs busy
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.endm
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.macro waituart, rd, rx
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wait: mrc p14, 0, pc, c0, c1, 0
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bcs wait
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.endm
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#elif defined(CONFIG_CPU_XSCALE)
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.macro senduart, rd, rx
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