crypto: omap-sham - Add code to use dmaengine API
Add code to use the new dmaengine API alongside the existing DMA code that uses the private OMAP DMA API. The API to use is chosen by defining or undefining 'OMAP_SHAM_DMA_PRIVATE'. This is a transitional change and the code that uses the private DMA API will be removed in an upcoming commit. CC: Russell King <rmk+kernel@arm.linux.org.uk> CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com> Signed-off-by: Mark A. Greer <mgreer@animalcreek.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Mark A. Greer
Herbert Xu
parent
3b3f440023
commit
dfd061d5a8
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@ -13,6 +13,8 @@
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* Some ideas are from old omap-sha1-md5.c driver.
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*/
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#define OMAP_SHAM_DMA_PRIVATE
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/err.h>
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@ -27,6 +29,8 @@
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/omap-dma.h>
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#include <linux/pm_runtime.h>
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#include <linux/delay.h>
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#include <linux/crypto.h>
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@ -37,15 +41,15 @@
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#include <crypto/hash.h>
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#include <crypto/internal/hash.h>
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#include <linux/omap-dma.h>
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#include <mach/irqs.h>
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#define SHA_REG_DIGEST(x) (0x00 + ((x) * 0x04))
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#define SHA_REG_DIN(x) (0x1C + ((x) * 0x04))
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#define SHA1_MD5_BLOCK_SIZE SHA1_BLOCK_SIZE
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#define MD5_DIGEST_SIZE 16
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#define DST_MAXBURST 16
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#define DMA_MIN (DST_MAXBURST * sizeof(u32))
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#define SHA_REG_DIGCNT 0x14
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#define SHA_REG_CTRL 0x18
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@ -109,6 +113,9 @@ struct omap_sham_reqctx {
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/* walk state */
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struct scatterlist *sg;
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#ifndef OMAP_SHAM_DMA_PRIVATE
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struct scatterlist sgl;
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#endif
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unsigned int offset; /* offset in current sg */
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unsigned int total; /* total request */
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@ -142,8 +149,12 @@ struct omap_sham_dev {
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int irq;
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spinlock_t lock;
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int err;
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#ifdef OMAP_SHAM_DMA_PRIVATE
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int dma;
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int dma_lch;
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#else
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struct dma_chan *dma_lch;
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#endif
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struct tasklet_struct done_task;
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unsigned long flags;
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@ -313,15 +324,32 @@ static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
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return -EINPROGRESS;
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}
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#ifndef OMAP_SHAM_DMA_PRIVATE
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static void omap_sham_dma_callback(void *param)
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{
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struct omap_sham_dev *dd = param;
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set_bit(FLAGS_DMA_READY, &dd->flags);
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tasklet_schedule(&dd->done_task);
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}
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#endif
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static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
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size_t length, int final)
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size_t length, int final, int is_sg)
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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#ifdef OMAP_SHAM_DMA_PRIVATE
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int len32;
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#else
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struct dma_async_tx_descriptor *tx;
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struct dma_slave_config cfg;
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int len32, ret;
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#endif
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dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
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ctx->digcnt, length, final);
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#ifdef OMAP_SHAM_DMA_PRIVATE
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len32 = DIV_ROUND_UP(length, sizeof(u32));
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omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
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@ -331,6 +359,50 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
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omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
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dma_addr, 0, 0);
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#else
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memset(&cfg, 0, sizeof(cfg));
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cfg.dst_addr = dd->phys_base + SHA_REG_DIN(0);
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.dst_maxburst = DST_MAXBURST;
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ret = dmaengine_slave_config(dd->dma_lch, &cfg);
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if (ret) {
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pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
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return ret;
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}
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len32 = DIV_ROUND_UP(length, DMA_MIN) * DMA_MIN;
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if (is_sg) {
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/*
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* The SG entry passed in may not have the 'length' member
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* set correctly so use a local SG entry (sgl) with the
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* proper value for 'length' instead. If this is not done,
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* the dmaengine may try to DMA the incorrect amount of data.
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*/
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sg_init_table(&ctx->sgl, 1);
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ctx->sgl.page_link = ctx->sg->page_link;
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ctx->sgl.offset = ctx->sg->offset;
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sg_dma_len(&ctx->sgl) = len32;
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sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
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tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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} else {
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tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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}
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if (!tx) {
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dev_err(dd->dev, "prep_slave_sg/single() failed\n");
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return -EINVAL;
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}
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tx->callback = omap_sham_dma_callback;
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tx->callback_param = dd;
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#endif
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omap_sham_write_ctrl(dd, length, final, 1);
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ctx->digcnt += length;
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@ -340,7 +412,12 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
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set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
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#ifdef OMAP_SHAM_DMA_PRIVATE
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omap_start_dma(dd->dma_lch);
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#else
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dmaengine_submit(tx);
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dma_async_issue_pending(dd->dma_lch);
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#endif
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return -EINPROGRESS;
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}
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@ -387,6 +464,8 @@ static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
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struct omap_sham_reqctx *ctx,
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size_t length, int final)
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{
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int ret;
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ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
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@ -396,8 +475,12 @@ static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
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ctx->flags &= ~BIT(FLAGS_SG);
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/* next call does not fail... so no unmap in the case of error */
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return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
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ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
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if (ret)
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dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
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DMA_TO_DEVICE);
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return ret;
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}
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static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
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@ -432,6 +515,7 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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unsigned int length, final, tail;
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struct scatterlist *sg;
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int ret;
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if (!ctx->total)
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return 0;
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@ -439,6 +523,17 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
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if (ctx->bufcnt || ctx->offset)
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return omap_sham_update_dma_slow(dd);
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#ifndef OMAP_SHAM_DMA_PRIVATE
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/*
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* Don't use the sg interface when the transfer size is less
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* than the number of elements in a DMA frame. Otherwise,
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* the dmaengine infrastructure will calculate that it needs
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* to transfer 0 frames which ultimately fails.
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*/
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if (ctx->total < (DST_MAXBURST * sizeof(u32)))
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return omap_sham_update_dma_slow(dd);
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#endif
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dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
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ctx->digcnt, ctx->bufcnt, ctx->total);
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@ -476,8 +571,11 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
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final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
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/* next call does not fail... so no unmap in the case of error */
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return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
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ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
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if (ret)
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dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
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return ret;
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}
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static int omap_sham_update_cpu(struct omap_sham_dev *dd)
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@ -496,7 +594,12 @@ static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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#ifdef OMAP_SHAM_DMA_PRIVATE
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omap_stop_dma(dd->dma_lch);
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#else
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dmaengine_terminate_all(dd->dma_lch);
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#endif
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if (ctx->flags & BIT(FLAGS_SG)) {
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dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
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if (ctx->sg->length == ctx->offset) {
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@ -583,7 +686,7 @@ static int omap_sham_final_req(struct omap_sham_dev *dd)
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struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
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int err = 0, use_dma = 1;
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if (ctx->bufcnt <= 64)
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if (ctx->bufcnt <= DMA_MIN)
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/* faster to handle last block with cpu */
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use_dma = 0;
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@ -699,6 +802,7 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
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if (err)
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goto err1;
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#ifdef OMAP_SHAM_DMA_PRIVATE
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omap_set_dma_dest_params(dd->dma_lch, 0,
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OMAP_DMA_AMODE_CONSTANT,
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dd->phys_base + SHA_REG_DIN(0), 0, 16);
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@ -708,6 +812,7 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
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omap_set_dma_src_burst_mode(dd->dma_lch,
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OMAP_DMA_DATA_BURST_4);
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#endif
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if (ctx->digcnt)
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/* request has changed - restore hash */
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@ -1099,6 +1204,7 @@ static irqreturn_t omap_sham_irq(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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#ifdef OMAP_SHAM_DMA_PRIVATE
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static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
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{
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struct omap_sham_dev *dd = data;
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@ -1136,12 +1242,17 @@ static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
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dd->dma_lch = -1;
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}
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}
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#endif
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static int __devinit omap_sham_probe(struct platform_device *pdev)
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{
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struct omap_sham_dev *dd;
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struct device *dev = &pdev->dev;
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struct resource *res;
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#ifndef OMAP_SHAM_DMA_PRIVATE
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dma_cap_mask_t mask;
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unsigned dma_chan;
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#endif
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int err, i, j;
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dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
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@ -1176,7 +1287,11 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
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err = -ENODEV;
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goto res_err;
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}
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#ifdef OMAP_SHAM_DMA_PRIVATE
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dd->dma = res->start;
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#else
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dma_chan = res->start;
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#endif
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/* Get the IRQ */
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dd->irq = platform_get_irq(pdev, 0);
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@ -1193,9 +1308,22 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
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goto res_err;
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}
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#ifdef OMAP_SHAM_DMA_PRIVATE
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err = omap_sham_dma_init(dd);
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if (err)
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goto dma_err;
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#else
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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dd->dma_lch = dma_request_channel(mask, omap_dma_filter_fn, &dma_chan);
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if (!dd->dma_lch) {
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dev_err(dev, "unable to obtain RX DMA engine channel %u\n",
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dma_chan);
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err = -ENXIO;
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goto dma_err;
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}
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#endif
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dd->io_base = ioremap(dd->phys_base, SZ_4K);
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if (!dd->io_base) {
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@ -1231,7 +1359,11 @@ err_algs:
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iounmap(dd->io_base);
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pm_runtime_disable(dev);
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io_err:
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#ifdef OMAP_SHAM_DMA_PRIVATE
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omap_sham_dma_cleanup(dd);
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#else
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dma_release_channel(dd->dma_lch);
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#endif
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dma_err:
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if (dd->irq >= 0)
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free_irq(dd->irq, dd);
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@ -1260,7 +1392,11 @@ static int __devexit omap_sham_remove(struct platform_device *pdev)
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tasklet_kill(&dd->done_task);
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iounmap(dd->io_base);
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pm_runtime_disable(&pdev->dev);
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#ifdef OMAP_SHAM_DMA_PRIVATE
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omap_sham_dma_cleanup(dd);
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#else
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dma_release_channel(dd->dma_lch);
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#endif
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if (dd->irq >= 0)
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free_irq(dd->irq, dd);
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kfree(dd);
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