drm/radeon/kms: respect single crtc cards, only create one crtc. (v2)
Also add single crtc for RN50 chips. changes in v2: fix vblank init to respect single crtc flag fix r100 mode bandwidth to respect single crtc flag Signed-off-by: Dave Airlie <airlied@redhat.com>
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185974dd59
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dfee5614e4
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@ -2135,9 +2135,11 @@ void r100_bandwidth_update(struct radeon_device *rdev)
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mode1 = &rdev->mode_info.crtcs[0]->base.mode;
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pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
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}
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if (rdev->mode_info.crtcs[1]->base.enabled) {
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mode2 = &rdev->mode_info.crtcs[1]->base.mode;
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pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
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if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
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if (rdev->mode_info.crtcs[1]->base.enabled) {
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mode2 = &rdev->mode_info.crtcs[1]->base.mode;
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pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
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}
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}
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min_mem_eff.full = rfixed_const_8(0);
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@ -724,7 +724,11 @@ int radeon_modeset_init(struct radeon_device *rdev)
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if (ret) {
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return ret;
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}
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/* allocate crtcs - TODO single crtc */
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if (rdev->flags & RADEON_SINGLE_CRTC)
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num_crtc = 1;
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/* allocate crtcs */
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for (i = 0; i < num_crtc; i++) {
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radeon_crtc_init(rdev->ddev, i);
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}
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@ -1345,6 +1345,7 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
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void
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radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct drm_encoder *encoder;
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struct radeon_encoder *radeon_encoder;
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@ -1364,7 +1365,10 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
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return;
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encoder = &radeon_encoder->base;
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encoder->possible_crtcs = 0x3;
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if (rdev->flags & RADEON_SINGLE_CRTC)
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encoder->possible_crtcs = 0x1;
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else
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encoder->possible_crtcs = 0x3;
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encoder->possible_clones = 0;
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radeon_encoder->enc_priv = NULL;
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@ -146,6 +146,7 @@ int radeonfb_create(struct drm_device *dev,
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unsigned long tmp;
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bool fb_tiled = false; /* useful for testing */
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u32 tiling_flags = 0;
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int crtc_count;
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mode_cmd.width = surface_width;
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mode_cmd.height = surface_height;
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@ -217,7 +218,11 @@ int radeonfb_create(struct drm_device *dev,
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rfbdev = info->par;
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rfbdev->helper.funcs = &radeon_fb_helper_funcs;
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rfbdev->helper.dev = dev;
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ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2,
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if (rdev->flags & RADEON_SINGLE_CRTC)
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crtc_count = 1;
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else
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crtc_count = 2;
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ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, crtc_count,
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RADEONFB_CONN_LIMIT);
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if (ret)
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goto out_unref;
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@ -83,8 +83,12 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
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int radeon_irq_kms_init(struct radeon_device *rdev)
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{
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int r = 0;
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int num_crtc = 2;
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r = drm_vblank_init(rdev->ddev, 2);
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if (rdev->flags & RADEON_SINGLE_CRTC)
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num_crtc = 1;
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r = drm_vblank_init(rdev->ddev, num_crtc);
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if (r) {
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return r;
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}
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@ -1318,7 +1318,10 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
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return;
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encoder = &radeon_encoder->base;
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encoder->possible_crtcs = 0x3;
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if (rdev->flags & RADEON_SINGLE_CRTC)
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encoder->possible_crtcs = 0x1;
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else
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encoder->possible_crtcs = 0x3;
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encoder->possible_clones = 0;
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radeon_encoder->enc_priv = NULL;
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@ -80,7 +80,7 @@
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{0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
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{0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
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{0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
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{0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
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{0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_SINGLE_CRTC}, \
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{0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
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{0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
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{0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
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@ -113,7 +113,7 @@
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{0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
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{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_SINGLE_CRTC}, \
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{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
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