ARM: sunxi: smp: Move assembly code into a file
Move the assembly code for cluster cache enabling and resuming into an assembly file instead of having it directly in C code. Remove the CFLAGS because we are using the ARM directive "arch" instead. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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@ -1,5 +1,5 @@
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CFLAGS_mc_smp.o += -march=armv7-a
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obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
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obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
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obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
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obj-$(CONFIG_SMP) += platsmp.o
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80
arch/arm/mach-sunxi/headsmp.S
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80
arch/arm/mach-sunxi/headsmp.S
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (c) 2018 Chen-Yu Tsai
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* Copyright (c) 2018 Bootlin
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*
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* Chen-Yu Tsai <wens@csie.org>
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* Mylène Josserand <mylene.josserand@bootlin.com>
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*
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* SMP support for sunxi based systems with Cortex A7/A15
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*
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/cputype.h>
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ENTRY(sunxi_mc_smp_cluster_cache_enable)
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.arch armv7-a
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*
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* Also enable regional clock gating and L2 data latency settings for
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* Cortex-A15. These settings are from the vendor kernel.
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*/
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mrc p15, 0, r1, c0, c0, 0
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movw r2, #(ARM_CPU_PART_MASK & 0xffff)
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movt r2, #(ARM_CPU_PART_MASK >> 16)
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and r1, r1, r2
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movw r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
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movt r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
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cmp r1, r2
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bne not_a15
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/* The following is Cortex-A15 specific */
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/* ACTLR2: Enable CPU regional clock gates */
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mrc p15, 1, r1, c15, c0, 4
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orr r1, r1, #(0x1 << 31)
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mcr p15, 1, r1, c15, c0, 4
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/* L2ACTLR */
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mrc p15, 1, r1, c15, c0, 0
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/* Enable L2, GIC, and Timer regional clock gates */
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orr r1, r1, #(0x1 << 26)
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/* Disable clean/evict from being pushed to external */
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orr r1, r1, #(0x1<<3)
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mcr p15, 1, r1, c15, c0, 0
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/* L2CTRL: L2 data RAM latency */
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mrc p15, 1, r1, c9, c0, 2
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bic r1, r1, #(0x7 << 0)
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orr r1, r1, #(0x3 << 0)
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mcr p15, 1, r1, c9, c0, 2
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/* End of Cortex-A15 specific setup */
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not_a15:
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/* Get value of sunxi_mc_smp_first_comer */
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adr r1, first
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ldr r0, [r1]
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ldr r0, [r1, r0]
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/* Skip cci_enable_port_for_self if not first comer */
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cmp r0, #0
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bxeq lr
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b cci_enable_port_for_self
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.align 2
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first: .word sunxi_mc_smp_first_comer - .
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ENDPROC(sunxi_mc_smp_cluster_cache_enable)
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ENTRY(sunxi_mc_smp_secondary_startup)
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bl sunxi_mc_smp_cluster_cache_enable
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b secondary_startup
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ENDPROC(sunxi_mc_smp_secondary_startup)
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ENTRY(sunxi_mc_smp_resume)
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bl sunxi_mc_smp_cluster_cache_enable
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b cpu_resume
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ENDPROC(sunxi_mc_smp_resume)
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@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
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static void __iomem *prcm_base;
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static void __iomem *sram_b_smp_base;
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extern void sunxi_mc_smp_secondary_startup(void);
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extern void sunxi_mc_smp_resume(void);
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static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
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{
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struct device_node *node;
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@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
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}
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static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
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static int sunxi_mc_smp_first_comer;
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*
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* Also enable regional clock gating and L2 data latency settings for
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* Cortex-A15. These settings are from the vendor kernel.
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*/
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static void __naked sunxi_mc_smp_cluster_cache_enable(void)
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{
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asm volatile (
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"mrc p15, 0, r1, c0, c0, 0\n"
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"movw r2, #" __stringify(ARM_CPU_PART_MASK & 0xffff) "\n"
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"movt r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
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"and r1, r1, r2\n"
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"movw r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0xffff) "\n"
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"movt r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
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"cmp r1, r2\n"
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"bne not_a15\n"
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/* The following is Cortex-A15 specific */
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/* ACTLR2: Enable CPU regional clock gates */
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"mrc p15, 1, r1, c15, c0, 4\n"
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"orr r1, r1, #(0x1<<31)\n"
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"mcr p15, 1, r1, c15, c0, 4\n"
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/* L2ACTLR */
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"mrc p15, 1, r1, c15, c0, 0\n"
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/* Enable L2, GIC, and Timer regional clock gates */
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"orr r1, r1, #(0x1<<26)\n"
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/* Disable clean/evict from being pushed to external */
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"orr r1, r1, #(0x1<<3)\n"
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"mcr p15, 1, r1, c15, c0, 0\n"
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/* L2CTRL: L2 data RAM latency */
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"mrc p15, 1, r1, c9, c0, 2\n"
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"bic r1, r1, #(0x7<<0)\n"
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"orr r1, r1, #(0x3<<0)\n"
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"mcr p15, 1, r1, c9, c0, 2\n"
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/* End of Cortex-A15 specific setup */
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"not_a15:\n"
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/* Get value of sunxi_mc_smp_first_comer */
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"adr r1, first\n"
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"ldr r0, [r1]\n"
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"ldr r0, [r1, r0]\n"
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/* Skip cci_enable_port_for_self if not first comer */
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"cmp r0, #0\n"
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"bxeq lr\n"
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"b cci_enable_port_for_self\n"
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".align 2\n"
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"first: .word sunxi_mc_smp_first_comer - .\n"
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);
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}
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static void __naked sunxi_mc_smp_secondary_startup(void)
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{
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asm volatile(
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"bl sunxi_mc_smp_cluster_cache_enable\n"
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"b secondary_startup"
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/* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
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:: "i" (sunxi_mc_smp_cluster_cache_enable)
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);
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}
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int sunxi_mc_smp_first_comer;
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static DEFINE_SPINLOCK(boot_lock);
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@ -637,16 +573,6 @@ static bool __init sunxi_mc_smp_cpu_table_init(void)
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*/
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typedef typeof(cpu_reset) phys_reset_t;
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static void __init __naked sunxi_mc_smp_resume(void)
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{
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asm volatile(
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"bl sunxi_mc_smp_cluster_cache_enable\n"
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"b cpu_resume"
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/* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
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:: "i" (sunxi_mc_smp_cluster_cache_enable)
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);
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}
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static int __init nocache_trampoline(unsigned long __unused)
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{
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phys_reset_t phys_reset;
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