ARM: exynos: Fix imprecise abort during Exynos5422 suspend to RAM
Suspend to RAM on Odroid XU3/XU4/HC1 family (Exynos5422) causes imprecise abort: PM: Syncing filesystems ... done. Freezing user space processes ... (elapsed 0.003 seconds) done. OOM killer disabled. Freezing remaining freezable tasks ... (elapsed 0.003 seconds) done. wake enabled for irq 139 Disabling non-boot CPUs ... IRQ51 no longer affine to CPU1 IRQ52 no longer affine to CPU2 IRQ53 no longer affine to CPU3 IRQ54 no longer affine to CPU4 IRQ55 no longer affine to CPU5 IRQ56 no longer affine to CPU6 cpu cpu4: Dropping the link to regulator.40 IRQ57 no longer affine to CPU7 Unhandled fault: external abort on non-linefetch (0x1008) at 0xf081a028 Internal error: : 1008 [#1] PREEMPT SMP ARM with last call trace in exynos_suspend_enter(). The abort is caused by writing to register in secure part of sysram. Boards booted under secure firmware (e.g. Hardkernel Odroid boards) should access non-secure sysram. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -26,6 +26,7 @@ Offset Value Purpose
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0x20 0xfcba0d10 (Magic cookie) AFTR
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0x24 exynos_cpu_resume_ns AFTR
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0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR
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0x28 0x0 or last value during resume (Exynos542x) System suspend
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2. Secure mode
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@ -110,6 +110,7 @@ void exynos_firmware_init(void);
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#define EXYNOS_SLEEP_MAGIC 0x00000bad
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#define EXYNOS_AFTR_MAGIC 0xfcba0d10
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bool __init exynos_secure_firmware_available(void);
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void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
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void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
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@ -185,7 +185,7 @@ static void exynos_l2_configure(const struct l2x0_regs *regs)
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exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
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}
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void __init exynos_firmware_init(void)
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bool __init exynos_secure_firmware_available(void)
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{
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struct device_node *nd;
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const __be32 *addr;
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@ -193,14 +193,22 @@ void __init exynos_firmware_init(void)
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nd = of_find_compatible_node(NULL, NULL,
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"samsung,secure-firmware");
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if (!nd)
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return;
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return false;
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addr = of_get_address(nd, 0, NULL, NULL);
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if (!addr) {
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pr_err("%s: No address specified.\n", __func__);
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return;
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return false;
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}
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return true;
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}
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void __init exynos_firmware_init(void)
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{
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if (!exynos_secure_firmware_available())
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return;
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pr_info("Running under secure firmware.\n");
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register_firmware_ops(&exynos_firmware_ops);
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@ -63,6 +63,7 @@ struct exynos_pm_data {
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struct exynos_pm_state {
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int cpu_state;
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unsigned int pmu_spare3;
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void __iomem *sysram_base;
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};
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static const struct exynos_pm_data *pm_data __ro_after_init;
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@ -261,7 +262,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
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writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
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mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
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@ -333,7 +334,7 @@ static void exynos5420_pm_prepare(void)
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* needs to restore it back in case, the primary cpu fails to
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* suspend for any reason.
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*/
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pm_state.cpu_state = readl_relaxed(sysram_base_addr +
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pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +
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EXYNOS5420_CPU_STATE);
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exynos_pm_enter_sleep_mode();
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@ -453,7 +454,7 @@ static void exynos5420_pm_resume(void)
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/* Restore the sysram cpu state register */
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writel_relaxed(pm_state.cpu_state,
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sysram_base_addr + EXYNOS5420_CPU_STATE);
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pm_state.sysram_base + EXYNOS5420_CPU_STATE);
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pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
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S5P_CENTRAL_SEQ_OPTION);
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@ -658,4 +659,13 @@ void __init exynos_pm_init(void)
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register_syscore_ops(&exynos_pm_syscore_ops);
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suspend_set_ops(&exynos_suspend_ops);
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/*
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* Applicable as of now only to Exynos542x. If booted under secure
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* firmware, the non-secure region of sysram should be used.
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*/
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if (exynos_secure_firmware_available())
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pm_state.sysram_base = sysram_ns_base_addr;
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else
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pm_state.sysram_base = sysram_base_addr;
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}
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