MLK-11376-02 ARM: imx: add MSL code for imx6qp
Add MSL code for i.MX6QP. Signed-off-by: Bai Ping <b51503@freescale.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>pull/10/head
Bai Ping
Jason Liu
parent
1e4ea5c1eb
commit
e118809d7e
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@ -1,5 +1,5 @@
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/*
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* Copyright 2011-2013 Freescale Semiconductor, Inc.
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* Copyright 2011-2015 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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@ -31,7 +31,8 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy",
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static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
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static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
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static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
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static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
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static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
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static const char *axi_sels[] = { "periph", "axi_alt_sel", };
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static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
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static const char *gpu_axi_sels[] = { "axi", "ahb", };
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static const char *pre_axi_sels[] = { "axi", "ahb", };
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@ -41,6 +42,8 @@ static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_p
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static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
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static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
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static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
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static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
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static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
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static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
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static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
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static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
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@ -95,11 +98,13 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
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static struct clk *clk[IMX6QDL_CLK_END];
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static struct clk_onecell_data clk_data;
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static void __iomem *ccm_base;
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static unsigned int const clks_init_on[] __initconst = {
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IMX6QDL_CLK_MMDC_CH0_AXI,
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IMX6QDL_CLK_ROM,
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IMX6QDL_CLK_ARM,
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IMX6QDL_CLK_OCRAM,
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};
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static struct clk_div_table clk_enet_ref_table[] = {
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@ -418,7 +423,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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struct device_node *np;
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void __iomem *anatop_base, *base;
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int i;
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int ret;
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clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
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@ -474,7 +478,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
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clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
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clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
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clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
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clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
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clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
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clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
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@ -545,23 +549,25 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
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}
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clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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np = ccm_node;
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base = of_iomap(np, 0);
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ccm_base = base;
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WARN_ON(!base);
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/* name reg shift width parent_names num_parents */
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clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
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clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
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clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
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clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
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clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
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clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
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clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
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clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
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clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
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clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
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clk[IMX6QDL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
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clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux_glitchless("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels));
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clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
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clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
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clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
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@ -588,14 +594,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
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clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
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disable_anatop_clocks(anatop_base);
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imx6q_mmdc_ch1_mask_handshake(base);
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if (clk_on_imx6qp()) {
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clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
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clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
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} else {
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disable_anatop_clocks(anatop_base);
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imx6q_mmdc_ch1_mask_handshake(base);
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/*
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* The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
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* bug. Set the muxes to the requested values before registering the
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@ -606,6 +611,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
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clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
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}
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clk[IMX6QDL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
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clk[IMX6QDL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
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clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
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clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
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clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
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@ -671,6 +678,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6);
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clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7);
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clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
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clk[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0", 1, 7);
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clk[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1", 1, 7);
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} else {
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clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
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clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
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@ -678,6 +687,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
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clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
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clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
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clk[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
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clk[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
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}
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if (clk_on_imx6dl())
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clk[IMX6QDL_CLK_MLB_PODF] = imx_clk_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3);
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@ -744,6 +755,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
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clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
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clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
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clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
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clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
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clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
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clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
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clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
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@ -761,7 +774,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
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clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
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clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
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clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4);
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clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
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clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
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clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
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clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
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@ -807,7 +820,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
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clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
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clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
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clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4);
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clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
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clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
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clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
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clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
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@ -854,11 +867,23 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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clk_register_clkdev(clk[IMX6QDL_CLK_GPT_IPG], "ipg", "imx-gpt.0");
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clk_register_clkdev(clk[IMX6QDL_CLK_GPT_IPG_PER], "per", "imx-gpt.0");
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clk_register_clkdev(clk[IMX6QDL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0");
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clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
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clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
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if (clk_on_imx6dl())
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if (clk_on_imx6dl()) {
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clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
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clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]);
|
||||
/* set epdc/pxp axi clock to 200Mhz */
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
|
||||
clk_set_rate(clk[IMX6QDL_CLK_IPU2], 200000000);
|
||||
} else {
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
|
||||
}
|
||||
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
|
|
@ -876,23 +901,47 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
*/
|
||||
clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clk[clks_init_on[i]]);
|
||||
|
||||
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
|
||||
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
|
||||
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
|
||||
/* gpu clock initilazation */
|
||||
/*
|
||||
* On mx6dl, 2d core clock sources(sel, podf) is from 3d
|
||||
* shader core clock, but 3d shader clock multiplexer of
|
||||
* mx6dl is different. For instance the equivalent of
|
||||
* pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl.
|
||||
* Make a note here.
|
||||
*/
|
||||
if (clk_on_imx6dl()) {
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 528000000);
|
||||
/* for mx6dl, change gpu3d_core parent to 594_PFD*/
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
|
||||
/* for mx6dl, change gpu2d_core parent to 594_PFD*/
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 528000000);
|
||||
} else if (clk_on_imx6q()) {
|
||||
if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL3_PFD0_720M]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 720000000);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 594000000);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_PFD0_720M]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 720000000);
|
||||
} else {
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 480000000);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Let's initially set up CLKO with OSC24M, since this configuration
|
||||
* is widely used by imx6q board designs to clock audio codec.
|
||||
*/
|
||||
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
|
||||
if (!ret)
|
||||
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
|
||||
if (ret)
|
||||
pr_warn("failed to set up CLKO: %d\n", ret);
|
||||
imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
|
||||
imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
|
||||
|
||||
/* Audio-related clocks configuration */
|
||||
clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
|
||||
|
|
@ -901,6 +950,39 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
if (IS_ENABLED(CONFIG_PCI_IMX6))
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
|
||||
|
||||
/* set eim_slow to 132Mhz */
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 132000000);
|
||||
|
||||
/*
|
||||
* Enable clocks only after both parent and rate are all initialized
|
||||
* as needed
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
imx_clk_prepare_enable(clk[clks_init_on[i]]);
|
||||
|
||||
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
|
||||
imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
|
||||
imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
|
||||
}
|
||||
|
||||
/*Set enet_ref clock to 125M to supply for RGMII tx_clk */
|
||||
clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000);
|
||||
|
||||
#ifdef CONFIG_MX6_VPU_352M
|
||||
/*
|
||||
* If VPU 352M is enabled, then PLL2_PDF2 need to be
|
||||
* set to 352M, cpufreq will be disabled as VDDSOC/PU
|
||||
* need to be at highest voltage, scaling cpu freq is
|
||||
* not saving any power, and busfreq will be also disabled
|
||||
* as the PLL2_PFD2 is not at default freq, in a word,
|
||||
* all modules that sourceing clk from PLL2_PFD2 will
|
||||
* be impacted.
|
||||
*/
|
||||
imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD2_396M], 352000000);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_VPU_AXI_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
|
||||
pr_info("VPU 352M is enabled!\n");
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize the GPU clock muxes, so that the maximum specified clock
|
||||
* rates for the respective SoC are not exceeded.
|
||||
|
|
@ -920,5 +1002,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
}
|
||||
CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -271,6 +271,13 @@
|
|||
#define IMX6QDL_CLK_PRE_AXI 258
|
||||
#define IMX6QDL_CLK_MLB_SEL 259
|
||||
#define IMX6QDL_CLK_MLB_PODF 260
|
||||
#define IMX6QDL_CLK_END 261
|
||||
#define IMX6QDL_CLK_AXI_ALT_SEL 261
|
||||
#define IMX6QDL_CLK_LDB_DI0_DIV_7 262
|
||||
#define IMX6QDL_CLK_LDB_DI1_DIV_7 263
|
||||
#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 264
|
||||
#define IMX6QDL_CLK_LDB_DI1_DIV_SEL 265
|
||||
#define IMX6QDL_CLK_DCIC1 266
|
||||
#define IMX6QDL_CLK_DCIC2 267
|
||||
#define IMX6QDL_CLK_END 268
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue