net: ethernet: renesas: sh_eth: add POST registers for rz
Due to a mistake in the hardware manual, the FWSLC and POST1-4 registers were not documented and left out of the driver for RZ/A making the CAM feature non-operational. Additionally, when the offset values for POST1-4 are left blank, the driver attempts to set them using an offset of 0xFFFF which can cause a memory corruption or panic. This patch fixes the panic and properly enables CAM. Reported-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -201,9 +201,14 @@ static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ARSTR] = 0x0000,
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[TSU_CTRST] = 0x0004,
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[TSU_FWSLC] = 0x0038,
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[TSU_VTAG0] = 0x0058,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TSU_ADRH0] = 0x0100,
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[TXNLCR0] = 0x0080,
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@ -2786,6 +2791,8 @@ static void sh_eth_tsu_init(struct sh_eth_private *mdp)
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{
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if (sh_eth_is_rz_fast_ether(mdp)) {
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sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
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sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
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TSU_FWSLC); /* Enable POST registers */
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return;
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}
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