ARM: OMAP5: l3: Add l3 error handler support for omap5
The l3 interconnect ip is same for OMAP4 and OMAP5. So reuse the l3 error handler error code for OMAP5 as well. Also a few targets has been newly added for OMAP5. So updating the driver for that here. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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@ -197,6 +197,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o
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# L3 interconnect
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obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
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obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
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obj-$(CONFIG_SOC_OMAP5) += omap_l3_noc.o
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obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
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mailbox_mach-objs := mailbox.o
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@ -84,7 +84,7 @@ static int __init omap4_l3_init(void)
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* To avoid code running on other OMAPs in
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* multi-omap builds
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*/
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if (!(cpu_is_omap44xx()))
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if (!cpu_is_omap44xx() && !soc_is_omap54xx())
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return -ENODEV;
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for (i = 0; i < L3_MODULES; i++) {
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@ -51,7 +51,9 @@ static u32 l3_targ_inst_clk1[] = {
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0x200, /* DMM2 */
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0x300, /* ABE */
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0x400, /* L4CFG */
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0x600 /* CLK2 PWR DISC */
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0x600, /* CLK2 PWR DISC */
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0x0, /* Host CLK1 */
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0x900 /* L4 Wakeup */
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};
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static u32 l3_targ_inst_clk2[] = {
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@ -72,11 +74,16 @@ static u32 l3_targ_inst_clk2[] = {
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0xE00, /* missing in TRM corresponds to AES2*/
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0xC00, /* L4 PER3 */
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0xA00, /* L4 PER1*/
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0xB00 /* L4 PER2*/
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0xB00, /* L4 PER2*/
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0x0, /* HOST CLK2 */
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0x1800, /* CAL */
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0x1700 /* LLI */
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};
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static u32 l3_targ_inst_clk3[] = {
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0x0100 /* EMUSS */
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0x0100 /* EMUSS */,
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0x0300, /* DEBUGSS_CT_TBR */
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0x0 /* HOST CLK3 */
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};
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static struct l3_masters_data {
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@ -110,13 +117,15 @@ static struct l3_masters_data {
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{ 0xC8, "USBHOSTFS"}
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};
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static char *l3_targ_inst_name[L3_MODULES][18] = {
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static char *l3_targ_inst_name[L3_MODULES][21] = {
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{
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"DMM1",
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"DMM2",
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"ABE",
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"L4CFG",
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"CLK2 PWR DISC",
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"HOST CLK1",
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"L4 WAKEUP"
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},
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{
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"CORTEX M3" ,
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@ -137,9 +146,14 @@ static char *l3_targ_inst_name[L3_MODULES][18] = {
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"L4 PER3",
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"L4 PER1",
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"L4 PER2",
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"HOST CLK2",
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"CAL",
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"LLI"
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},
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{
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"EMUSS",
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"DEBUG SOURCE",
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"HOST CLK3"
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},
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};
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