MLK-18789-5: ARM64: dts: imx8dx: Add dts file for lcdif
Add nodes for the ADMA eLCDIF controller found in i.MX8QXP and specific dts file for it's usage with the Seiko 43WVF1G LCD panel. Signed-off-by: Robert Chiras <robert.chiras@nxp.com>pull/10/head
Robert Chiras
Jason Liu
parent
37b999a6c0
commit
e1954f7426
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@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
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fsl-imx8qxp-mek-enet2-tja1100.dtb \
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fsl-imx8qxp-mek-dsi-rm67191.dtb \
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fsl-imx8qxp-mek-a0.dtb \
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fsl-imx8qxp-mek-lcdif.dtb \
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fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dtb \
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fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dtb \
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fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \
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@ -821,6 +821,20 @@
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#address-cells = <1>;
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#size-cells = <0>;
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pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
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reg = <SC_R_ELCDIF_PLL>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_dma_lcd0: PD_DMA_LCD_0 {
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reg = <SC_R_LCD_0>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma_elcdif_pll>;
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};
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};
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pd_dma_flexcan0: PD_DMA_CAN_0 {
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reg = <SC_R_CAN_0>;
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#power-domain-cells = <0>;
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@ -982,20 +996,6 @@
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
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reg = <SC_R_ELCDIF_PLL>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_dma_lcd0: PD_DMA_LCD_0 {
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reg = <SC_R_LCD_0>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma_elcdif_pll>;
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};
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};
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};
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pd_gpu: gpu-power-domain {
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@ -1747,6 +1747,32 @@
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power-domains = <&pd_mipi_dsi0>;
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};
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adma_lcdif: lcdif@5a180000 {
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compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
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reg = <0x0 0x5a180000 0x0 0x10000>;
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clocks = <&clk IMX8QXP_LCD_CLK>, <&clk IMX8QXP_LCD_IPG_CLK>;
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clock-names = "pix", "disp_axi";
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assigned-clocks = <&clk IMX8QXP_LCD_SEL>, <&clk IMX8QXP_ELCDIF_PLL>;
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assigned-clock-rates = <804000000>, <804000000>;
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assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd_dma_lcd0>;
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status = "disabled";
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};
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pwm_adma_lcdif: pwm@5a190000 {
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compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
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reg = <0x0 0x5a190000 0 0x1000>;
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clocks = <&clk IMX8QXP_PWM_IPG_CLK>,
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<&clk IMX8QXP_PWM_CLK>;
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clock-names = "ipg", "per";
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assigned-clocks = <&clk IMX8QXP_PWM_CLK>;
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assigned-clock-rates = <24000000>;
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#pwm-cells = <2>;
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power-domains = <&pd_dma_pwm0>;
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status = "disabled";
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};
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mipi_dsi_csr1: csr@56221000 {
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compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon";
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reg = <0x0 0x56221000 0x0 0x1000>;
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@ -0,0 +1,85 @@
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/*
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* Copyright 2018 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "fsl-imx8qxp-mek.dts"
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/ {
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display-subsystem {
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status = "disabled";
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};
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panel {
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compatible = "sii,43wvf1g";
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backlight = <&lcdif_backlight>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&adapter_out>;
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};
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};
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};
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seiko_adapter: seiko-adapter {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,seiko-43wvfig";
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bus_mode = <18>;
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port@0 {
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reg = <0>;
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adapter_in: endpoint {
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remote-endpoint = <&lcdif_out>;
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};
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};
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port@1 {
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reg = <1>;
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adapter_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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&esai0 {
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status = "disabled";
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};
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&sai1 {
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status = "disabled";
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};
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&lpuart1 {
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status = "disabled";
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};
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&lcdif_backlight {
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status = "okay";
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};
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&adma_lcdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif>;
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status = "okay";
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port@0 {
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lcdif_out: lcdif-endpoint {
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remote-endpoint = <&adapter_in>;
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};
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};
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};
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&pwm_adma_lcdif {
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status = "okay";
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};
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@ -192,6 +192,16 @@
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100>;
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default-brightness-level = <80>;
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};
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lcdif_backlight: lcdif_backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm_adma_lcdif 0 100000 0>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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status = "disabled";
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};
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};
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&acm {
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@ -254,7 +264,9 @@
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imx8qxp-mek {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* TODO: conflicts with LCDIF!!!
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SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c
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*/
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SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
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>;
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};
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@ -363,6 +375,46 @@
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>;
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};
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pinctrl_lcdif: lcdif_grp {
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fsl,pins = <
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SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060
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SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x00000060
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SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060
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SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060
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SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060
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SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060
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SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060
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SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060
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SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060
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SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060
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SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060
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SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060
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SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060
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SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x00000060
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SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x00000060
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SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x00000060
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SC_P_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060
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SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060
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SC_P_SAI0_TXD_ADMA_LCDIF_D18 0x00000060
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SC_P_SAI0_TXC_ADMA_LCDIF_D19 0x00000060
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SC_P_SAI0_RXD_ADMA_LCDIF_D20 0x00000060
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SC_P_SAI1_RXD_ADMA_LCDIF_D21 0x00000060
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SC_P_SAI1_RXC_ADMA_LCDIF_D22 0x00000060
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SC_P_SAI1_RXFS_ADMA_LCDIF_D23 0x00000060
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SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060
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SC_P_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060
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SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000060
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SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060
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SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060
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>;
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};
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pinctrl_lcdif_pwm: lcdif_pwm_grp {
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fsl,pins = <
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SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060
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>;
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};
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pinctrl_flexspi0: flexspi0grp {
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fsl,pins = <
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SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
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@ -1148,6 +1200,13 @@
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status = "okay";
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};
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&pwm_adma_lcdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif_pwm>;
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status = "okay";
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};
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/* DSI/LVDS port 1 */
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&i2c0_mipi_lvds1 {
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#address-cells = <1>;
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