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drm/nouveau/pmu/gk110: implement gr power-up magic like PGOB on earlier chips

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Turns out the PTHERM part of this dance is bracketed by the same PMU
fiddling that occurs on GK104/6, let's assume it's also PGOB.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-03-20 15:20:17 +10:00
parent d9da545e10
commit e1fc44fb9d
7 changed files with 101 additions and 44 deletions
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1
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
View file

@ -35,6 +35,7 @@ extern struct nvkm_oclass *gt215_pmu_oclass;
extern struct nvkm_oclass *gf100_pmu_oclass;
extern struct nvkm_oclass *gf110_pmu_oclass;
extern struct nvkm_oclass *gk104_pmu_oclass;
extern struct nvkm_oclass *gk110_pmu_oclass;
extern struct nvkm_oclass *gk208_pmu_oclass;
extern struct nvkm_oclass *gk20a_pmu_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View file

@ -202,7 +202,7 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@ -236,7 +236,7 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View file

@ -124,11 +124,8 @@ void gf100_gr_dtor(struct nvkm_object *);
int gf100_gr_init(struct nvkm_object *);
void gf100_gr_zbc_init(struct gf100_gr_priv *);
int gk104_gr_fini(struct nvkm_object *, bool);
int gk104_gr_init(struct nvkm_object *);
int gk110_gr_fini(struct nvkm_object *, bool);
extern struct nvkm_ofuncs gf100_fermi_ofuncs;
extern struct nvkm_oclass gf100_gr_sclass[];

39
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
View file

@ -173,43 +173,6 @@ gk110_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
int
gk110_gr_fini(struct nvkm_object *object, bool suspend)
{
struct gf100_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
} magic[] = {
{ 0x020520, 0xfffffffc },
{ 0x020524, 0xfffffffe },
{ 0x020524, 0xfffffffc },
{ 0x020524, 0xfffffff8 },
{ 0x020524, 0xffffffe0 },
{ 0x020530, 0xfffffffe },
{ 0x02052c, 0xfffffffa },
{ 0x02052c, 0xfffffff0 },
{ 0x02052c, 0xffffffc0 },
{ 0x02052c, 0xffffff00 },
{ 0x02052c, 0xfffffc00 },
{ 0x02052c, 0xfffcfc00 },
{ 0x02052c, 0xfff0fc00 },
{ 0x02052c, 0xff80fc00 },
{ 0x020528, 0xfffffffe },
{ 0x020528, 0xfffffffc },
};
int i;
nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
for (i = 0; i < ARRAY_SIZE(magic); i++) {
nv_wr32(priv, magic[i].addr, magic[i].data);
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
return nvkm_gr_fini(&priv->base, suspend);
}
#include "fuc/hubgk110.fuc3.h"
struct gf100_gr_ucode
@ -237,7 +200,7 @@ gk110_gr_oclass = &(struct gf100_gr_oclass) {
.ctor = gf100_gr_ctor,
.dtor = gf100_gr_dtor,
.init = gk104_gr_init,
.fini = gk110_gr_fini,
.fini = _nvkm_gr_fini,
},
.cclass = &gk110_grctx_oclass,
.sclass = gk110_gr_sclass,

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
View file

@ -105,7 +105,7 @@ gk110b_gr_oclass = &(struct gf100_gr_oclass) {
.ctor = gf100_gr_ctor,
.dtor = gf100_gr_dtor,
.init = gk104_gr_init,
.fini = gk110_gr_fini,
.fini = _nvkm_gr_fini,
},
.cclass = &gk110b_grctx_oclass,
.sclass = gk110_gr_sclass,

1
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
View file

@ -4,5 +4,6 @@ nvkm-y += nvkm/subdev/pmu/gt215.o
nvkm-y += nvkm/subdev/pmu/gf100.o
nvkm-y += nvkm/subdev/pmu/gf110.o
nvkm-y += nvkm/subdev/pmu/gk104.o
nvkm-y += nvkm/subdev/pmu/gk110.o
nvkm-y += nvkm/subdev/pmu/gk208.o
nvkm-y += nvkm/subdev/pmu/gk20a.o

95
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c Normal file
View file

@ -0,0 +1,95 @@
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#define gf110_pmu_code gk110_pmu_code
#define gf110_pmu_data gk110_pmu_data
#include "priv.h"
#include "fuc/gf110.fuc4.h"
#include <subdev/timer.h>
static void
gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
{
static const struct {
u32 addr;
u32 data;
} magic[] = {
{ 0x020520, 0xfffffffc },
{ 0x020524, 0xfffffffe },
{ 0x020524, 0xfffffffc },
{ 0x020524, 0xfffffff8 },
{ 0x020524, 0xffffffe0 },
{ 0x020530, 0xfffffffe },
{ 0x02052c, 0xfffffffa },
{ 0x02052c, 0xfffffff0 },
{ 0x02052c, 0xffffffc0 },
{ 0x02052c, 0xffffff00 },
{ 0x02052c, 0xfffffc00 },
{ 0x02052c, 0xfffcfc00 },
{ 0x02052c, 0xfff0fc00 },
{ 0x02052c, 0xff80fc00 },
{ 0x020528, 0xfffffffe },
{ 0x020528, 0xfffffffc },
};
int i;
nv_mask(pmu, 0x000200, 0x00001000, 0x00000000);
nv_rd32(pmu, 0x000200);
nv_mask(pmu, 0x000200, 0x08000000, 0x08000000);
msleep(50);
nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000002);
nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
nv_mask(pmu, 0x0206b4, 0x00000000, 0x00000000);
for (i = 0; i < ARRAY_SIZE(magic); i++) {
nv_wr32(pmu, magic[i].addr, magic[i].data);
nv_wait(pmu, magic[i].addr, 0x80000000, 0x00000000);
}
nv_mask(pmu, 0x10a78c, 0x00000002, 0x00000000);
nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000001);
nv_mask(pmu, 0x10a78c, 0x00000001, 0x00000000);
nv_mask(pmu, 0x000200, 0x08000000, 0x00000000);
nv_mask(pmu, 0x000200, 0x00001000, 0x00001000);
nv_rd32(pmu, 0x000200);
}
struct nvkm_oclass *
gk110_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xf0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_pmu_ctor,
.dtor = _nvkm_pmu_dtor,
.init = _nvkm_pmu_init,
.fini = _nvkm_pmu_fini,
},
.code.data = gk110_pmu_code,
.code.size = sizeof(gk110_pmu_code),
.data.data = gk110_pmu_data,
.data.size = sizeof(gk110_pmu_data),
.pgob = gk110_pmu_pgob,
}.base;