Revert "ACPICA: FADT support cleanup"
Pavel Machek reports that commitsteinar/wifi_calib_4_9_kernel6ea8c546f3(ACPICA: FADT support cleanup) breaks thermal management on his Thinkpad X60 and T40p, so revert it. Link: https://bugzilla.kernel.org/show_bug.cgi?id=187311 Fixes:6ea8c546f3(ACPICA: FADT support cleanup) Reported-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Rafael J. Wysocki
parent
a25f0944ba
commit
e2174b0c24
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@ -480,19 +480,17 @@ static void acpi_tb_convert_fadt(void)
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u32 i;
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/*
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* For ACPI 1.0 FADTs (revision 1), ensure that reserved fields which
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* For ACPI 1.0 FADTs (revision 1 or 2), ensure that reserved fields which
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* should be zero are indeed zero. This will workaround BIOSs that
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* inadvertently place values in these fields.
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*
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* The ACPI 1.0 reserved fields that will be zeroed are the bytes located
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* at offset 45, 55, 95, and the word located at offset 109, 110.
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*
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* Note: The FADT revision value is unreliable because of BIOS errors.
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* The table length is instead used as the final word on the version.
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*
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* Note: FADT revision 3 is the ACPI 2.0 version of the FADT.
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* Note: The FADT revision value is unreliable. Only the length can be
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* trusted.
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*/
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if (acpi_gbl_FADT.header.length <= ACPI_FADT_V3_SIZE) {
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if (acpi_gbl_FADT.header.length <= ACPI_FADT_V2_SIZE) {
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acpi_gbl_FADT.preferred_profile = 0;
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acpi_gbl_FADT.pstate_control = 0;
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acpi_gbl_FADT.cst_control = 0;
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@ -230,72 +230,62 @@ struct acpi_table_facs {
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/* Fields common to all versions of the FADT */
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struct acpi_table_fadt {
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struct acpi_table_header header; /* [V1] Common ACPI table header */
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u32 facs; /* [V1] 32-bit physical address of FACS */
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u32 dsdt; /* [V1] 32-bit physical address of DSDT */
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u8 model; /* [V1] System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */
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u8 preferred_profile; /* [V1] Conveys preferred power management profile to OSPM. */
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u16 sci_interrupt; /* [V1] System vector of SCI interrupt */
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u32 smi_command; /* [V1] 32-bit Port address of SMI command port */
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u8 acpi_enable; /* [V1] Value to write to SMI_CMD to enable ACPI */
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u8 acpi_disable; /* [V1] Value to write to SMI_CMD to disable ACPI */
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u8 s4_bios_request; /* [V1] Value to write to SMI_CMD to enter S4BIOS state */
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u8 pstate_control; /* [V1] Processor performance state control */
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u32 pm1a_event_block; /* [V1] 32-bit port address of Power Mgt 1a Event Reg Blk */
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u32 pm1b_event_block; /* [V1] 32-bit port address of Power Mgt 1b Event Reg Blk */
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u32 pm1a_control_block; /* [V1] 32-bit port address of Power Mgt 1a Control Reg Blk */
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u32 pm1b_control_block; /* [V1] 32-bit port address of Power Mgt 1b Control Reg Blk */
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u32 pm2_control_block; /* [V1] 32-bit port address of Power Mgt 2 Control Reg Blk */
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u32 pm_timer_block; /* [V1] 32-bit port address of Power Mgt Timer Ctrl Reg Blk */
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u32 gpe0_block; /* [V1] 32-bit port address of General Purpose Event 0 Reg Blk */
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u32 gpe1_block; /* [V1] 32-bit port address of General Purpose Event 1 Reg Blk */
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u8 pm1_event_length; /* [V1] Byte Length of ports at pm1x_event_block */
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u8 pm1_control_length; /* [V1] Byte Length of ports at pm1x_control_block */
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u8 pm2_control_length; /* [V1] Byte Length of ports at pm2_control_block */
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u8 pm_timer_length; /* [V1] Byte Length of ports at pm_timer_block */
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u8 gpe0_block_length; /* [V1] Byte Length of ports at gpe0_block */
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u8 gpe1_block_length; /* [V1] Byte Length of ports at gpe1_block */
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u8 gpe1_base; /* [V1] Offset in GPE number space where GPE1 events start */
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u8 cst_control; /* [V1] Support for the _CST object and C-States change notification */
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u16 c2_latency; /* [V1] Worst case HW latency to enter/exit C2 state */
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u16 c3_latency; /* [V1] Worst case HW latency to enter/exit C3 state */
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u16 flush_size; /* [V1] Processor memory cache line width, in bytes */
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u16 flush_stride; /* [V1] Number of flush strides that need to be read */
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u8 duty_offset; /* [V1] Processor duty cycle index in processor P_CNT reg */
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u8 duty_width; /* [V1] Processor duty cycle value bit width in P_CNT register */
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u8 day_alarm; /* [V1] Index to day-of-month alarm in RTC CMOS RAM */
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u8 month_alarm; /* [V1] Index to month-of-year alarm in RTC CMOS RAM */
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u8 century; /* [V1] Index to century in RTC CMOS RAM */
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u16 boot_flags; /* [V3] IA-PC Boot Architecture Flags (see below for individual flags) */
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u8 reserved; /* [V1] Reserved, must be zero */
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u32 flags; /* [V1] Miscellaneous flag bits (see below for individual flags) */
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/* End of Version 1 FADT fields (ACPI 1.0) */
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struct acpi_generic_address reset_register; /* [V3] 64-bit address of the Reset register */
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u8 reset_value; /* [V3] Value to write to the reset_register port to reset the system */
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u16 arm_boot_flags; /* [V5] ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
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u8 minor_revision; /* [V5] FADT Minor Revision (ACPI 5.1) */
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u64 Xfacs; /* [V3] 64-bit physical address of FACS */
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u64 Xdsdt; /* [V3] 64-bit physical address of DSDT */
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struct acpi_generic_address xpm1a_event_block; /* [V3] 64-bit Extended Power Mgt 1a Event Reg Blk address */
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struct acpi_generic_address xpm1b_event_block; /* [V3] 64-bit Extended Power Mgt 1b Event Reg Blk address */
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struct acpi_generic_address xpm1a_control_block; /* [V3] 64-bit Extended Power Mgt 1a Control Reg Blk address */
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struct acpi_generic_address xpm1b_control_block; /* [V3] 64-bit Extended Power Mgt 1b Control Reg Blk address */
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struct acpi_generic_address xpm2_control_block; /* [V3] 64-bit Extended Power Mgt 2 Control Reg Blk address */
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struct acpi_generic_address xpm_timer_block; /* [V3] 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
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struct acpi_generic_address xgpe0_block; /* [V3] 64-bit Extended General Purpose Event 0 Reg Blk address */
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struct acpi_generic_address xgpe1_block; /* [V3] 64-bit Extended General Purpose Event 1 Reg Blk address */
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/* End of Version 3 FADT fields (ACPI 2.0) */
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struct acpi_generic_address sleep_control; /* [V4] 64-bit Sleep Control register (ACPI 5.0) */
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/* End of Version 4 FADT fields (ACPI 3.0 and ACPI 4.0) (Field was originally reserved in ACPI 3.0) */
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struct acpi_generic_address sleep_status; /* [V5] 64-bit Sleep Status register (ACPI 5.0) */
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/* End of Version 5 FADT fields (ACPI 5.0) */
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u64 hypervisor_id; /* [V6] Hypervisor Vendor ID (ACPI 6.0) */
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/* End of Version 6 FADT fields (ACPI 6.0) */
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struct acpi_table_header header; /* Common ACPI table header */
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u32 facs; /* 32-bit physical address of FACS */
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u32 dsdt; /* 32-bit physical address of DSDT */
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u8 model; /* System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */
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u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */
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u16 sci_interrupt; /* System vector of SCI interrupt */
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u32 smi_command; /* 32-bit Port address of SMI command port */
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u8 acpi_enable; /* Value to write to SMI_CMD to enable ACPI */
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u8 acpi_disable; /* Value to write to SMI_CMD to disable ACPI */
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u8 s4_bios_request; /* Value to write to SMI_CMD to enter S4BIOS state */
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u8 pstate_control; /* Processor performance state control */
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u32 pm1a_event_block; /* 32-bit port address of Power Mgt 1a Event Reg Blk */
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u32 pm1b_event_block; /* 32-bit port address of Power Mgt 1b Event Reg Blk */
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u32 pm1a_control_block; /* 32-bit port address of Power Mgt 1a Control Reg Blk */
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u32 pm1b_control_block; /* 32-bit port address of Power Mgt 1b Control Reg Blk */
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u32 pm2_control_block; /* 32-bit port address of Power Mgt 2 Control Reg Blk */
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u32 pm_timer_block; /* 32-bit port address of Power Mgt Timer Ctrl Reg Blk */
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u32 gpe0_block; /* 32-bit port address of General Purpose Event 0 Reg Blk */
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u32 gpe1_block; /* 32-bit port address of General Purpose Event 1 Reg Blk */
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u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */
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u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */
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u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */
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u8 pm_timer_length; /* Byte Length of ports at pm_timer_block */
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u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */
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u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */
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u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */
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u8 cst_control; /* Support for the _CST object and C-States change notification */
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u16 c2_latency; /* Worst case HW latency to enter/exit C2 state */
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u16 c3_latency; /* Worst case HW latency to enter/exit C3 state */
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u16 flush_size; /* Processor memory cache line width, in bytes */
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u16 flush_stride; /* Number of flush strides that need to be read */
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u8 duty_offset; /* Processor duty cycle index in processor P_CNT reg */
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u8 duty_width; /* Processor duty cycle value bit width in P_CNT register */
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u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */
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u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */
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u8 century; /* Index to century in RTC CMOS RAM */
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u16 boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */
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u8 reserved; /* Reserved, must be zero */
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u32 flags; /* Miscellaneous flag bits (see below for individual flags) */
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struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */
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u8 reset_value; /* Value to write to the reset_register port to reset the system */
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u16 arm_boot_flags; /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
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u8 minor_revision; /* FADT Minor Revision (ACPI 5.1) */
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u64 Xfacs; /* 64-bit physical address of FACS */
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u64 Xdsdt; /* 64-bit physical address of DSDT */
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struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
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struct acpi_generic_address xpm1b_event_block; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
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struct acpi_generic_address xpm1a_control_block; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
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struct acpi_generic_address xpm1b_control_block; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
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struct acpi_generic_address xpm2_control_block; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
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struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
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struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
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struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
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struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */
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struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */
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u64 hypervisor_id; /* Hypervisor Vendor ID (ACPI 6.0) */
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};
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/* Masks for FADT IA-PC Boot Architecture Flags (boot_flags) [Vx]=Introduced in this FADT revision */
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@ -311,8 +301,8 @@ struct acpi_table_fadt {
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/* Masks for FADT ARM Boot Architecture Flags (arm_boot_flags) ACPI 5.1 */
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#define ACPI_FADT_PSCI_COMPLIANT (1) /* 00: [V5] PSCI 0.2+ is implemented */
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#define ACPI_FADT_PSCI_USE_HVC (1<<1) /* 01: [V5] HVC must be used instead of SMC as the PSCI conduit */
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#define ACPI_FADT_PSCI_COMPLIANT (1) /* 00: [V5+] PSCI 0.2+ is implemented */
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#define ACPI_FADT_PSCI_USE_HVC (1<<1) /* 01: [V5+] HVC must be used instead of SMC as the PSCI conduit */
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/* Masks for FADT flags */
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@ -409,34 +399,20 @@ struct acpi_table_desc {
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* match the expected length. In other words, the length of the
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* FADT is the bottom line as to what the version really is.
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*
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* NOTE: There is no officialy released V2 of the FADT. This
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* version was used only for prototyping and testing during the
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* 32-bit to 64-bit transition. V3 was the first official 64-bit
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* version of the FADT.
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*
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* Update this list of defines when a new version of the FADT is
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* added to the ACPI specification. Note that the FADT version is
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* only incremented when new fields are appended to the existing
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* version. Therefore, the FADT version is competely independent
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* from the version of the ACPI specification where it is
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* defined.
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*
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* For reference, the various FADT lengths are as follows:
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* FADT V1 size: 0x074 ACPI 1.0
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* FADT V3 size: 0x0F4 ACPI 2.0
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* FADT V4 size: 0x100 ACPI 3.0 and ACPI 4.0
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* FADT V5 size: 0x10C ACPI 5.0
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* FADT V6 size: 0x114 ACPI 6.0
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* For reference, the values below are as follows:
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* FADT V1 size: 0x074
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* FADT V2 size: 0x084
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* FADT V3 size: 0x0F4
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* FADT V4 size: 0x0F4
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* FADT V5 size: 0x10C
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* FADT V6 size: 0x114
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*/
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#define ACPI_FADT_V1_SIZE (u32) (ACPI_FADT_OFFSET (flags) + 4) /* ACPI 1.0 */
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#define ACPI_FADT_V3_SIZE (u32) (ACPI_FADT_OFFSET (sleep_control)) /* ACPI 2.0 */
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#define ACPI_FADT_V4_SIZE (u32) (ACPI_FADT_OFFSET (sleep_status)) /* ACPI 3.0 and ACPI 4.0 */
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#define ACPI_FADT_V5_SIZE (u32) (ACPI_FADT_OFFSET (hypervisor_id)) /* ACPI 5.0 */
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#define ACPI_FADT_V6_SIZE (u32) (sizeof (struct acpi_table_fadt)) /* ACPI 6.0 */
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#define ACPI_FADT_V1_SIZE (u32) (ACPI_FADT_OFFSET (flags) + 4)
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#define ACPI_FADT_V2_SIZE (u32) (ACPI_FADT_OFFSET (minor_revision) + 1)
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#define ACPI_FADT_V3_SIZE (u32) (ACPI_FADT_OFFSET (sleep_control))
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#define ACPI_FADT_V5_SIZE (u32) (ACPI_FADT_OFFSET (hypervisor_id))
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#define ACPI_FADT_V6_SIZE (u32) (sizeof (struct acpi_table_fadt))
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/* Update these when new FADT versions are added */
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#define ACPI_FADT_MAX_VERSION 6
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#define ACPI_FADT_CONFORMANCE "ACPI 6.1 (FADT version 6)"
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#endif /* __ACTBL_H__ */
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