powerpc/44x: Warp patches for the new NDFC driver
Convert the Warp platform to use the newly merged NDFC driver - warp.dts changed to work with ndfc - warp-nand.c no longer needed - removed obsolete rev A support from cuboot-warp.c Signed-off-by: Sean MacLennan <smaclennan@pikatech.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>wifi-calibration
Sean MacLennan
Josh Boyer
parent
94ce1c585e
commit
e275e023aa
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@ -18,57 +18,14 @@
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static bd_t bd;
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static void warp_fixup_one_nor(u32 from, u32 to)
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{
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void *devp;
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char name[50];
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u32 v[2];
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sprintf(name, "/plb/opb/ebc/nor_flash@0,0/partition@%x", from);
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devp = finddevice(name);
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if (!devp)
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return;
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if (getprop(devp, "reg", v, sizeof(v)) == sizeof(v)) {
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v[0] = to;
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setprop(devp, "reg", v, sizeof(v));
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printf("NOR 64M fixup %x -> %x\r\n", from, to);
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}
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}
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static void warp_fixups(void)
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{
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ibm440ep_fixup_clocks(66000000, 11059200, 50000000);
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ibm4xx_sdram_fixup_memsize();
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ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
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dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
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/* Fixup for 64M flash on Rev A boards. */
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if (bd.bi_flashsize == 0x4000000) {
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void *devp;
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u32 v[3];
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devp = finddevice("/plb/opb/ebc/nor_flash@0,0");
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if (!devp)
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return;
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/* Fixup the size */
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if (getprop(devp, "reg", v, sizeof(v)) == sizeof(v)) {
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v[2] = bd.bi_flashsize;
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setprop(devp, "reg", v, sizeof(v));
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}
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/* Fixup parition offsets */
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warp_fixup_one_nor(0x300000, 0x3f00000);
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warp_fixup_one_nor(0x340000, 0x3f40000);
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warp_fixup_one_nor(0x380000, 0x3f80000);
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}
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}
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void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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@ -149,12 +149,17 @@
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reg = <0x00000002 0x00004000 0x00000A00>;
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};
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nor_flash@0,0 {
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nor@0,0 {
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compatible = "amd,s29gl032a", "cfi-flash";
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bank-width = <2>;
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reg = <0x00000000 0x00000000 0x00400000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "splash";
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reg = <0x00000000 0x00020000>;
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};
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partition@300000 {
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label = "fpga";
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reg = <0x0300000 0x00040000>;
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@ -168,6 +173,41 @@
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reg = <0x0380000 0x00080000>;
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};
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};
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ndfc@1,0 {
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compatible = "ibm,ndfc";
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reg = <0x00000001 0x00000000 0x00002000>;
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ccr = <0x00001000>;
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bank-settings = <0x80002222>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand {
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x00200000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x00200000 0x03E00000>;
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};
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partition@40000000 {
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label = "persistent";
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reg = <0x04000000 0x04000000>;
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};
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partition@80000000 {
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label = "persistent1";
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reg = <0x08000000 0x04000000>;
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};
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partition@C0000000 {
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label = "persistent2";
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reg = <0x0C000000 0x04000000>;
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};
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};
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};
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};
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UART0: serial@ef600300 {
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@ -3,5 +3,4 @@ obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
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obj-$(CONFIG_EBONY) += ebony.o
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obj-$(CONFIG_SAM440EP) += sam440ep.o
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obj-$(CONFIG_WARP) += warp.o
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obj-$(CONFIG_WARP) += warp-nand.o
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obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
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@ -1,135 +0,0 @@
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/*
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* PIKA Warp(tm) NAND flash specific routines
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*
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* Copyright (c) 2008 PIKA Technologies
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* Sean MacLennan <smaclennan@pikatech.com>
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*/
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/ndfc.h>
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#include <linux/of.h>
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#include <asm/machdep.h>
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#ifdef CONFIG_MTD_NAND_NDFC
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#define CS_NAND_0 1 /* use chip select 1 for NAND device 0 */
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#define WARP_NAND_FLASH_REG_ADDR 0xD0000000UL
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#define WARP_NAND_FLASH_REG_SIZE 0x2000
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static struct resource warp_ndfc = {
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.start = WARP_NAND_FLASH_REG_ADDR,
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.end = WARP_NAND_FLASH_REG_ADDR + WARP_NAND_FLASH_REG_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct mtd_partition nand_parts[] = {
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{
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.name = "kernel",
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.offset = 0,
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.size = 0x0200000
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},
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{
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.name = "root",
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.offset = 0x0200000,
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.size = 0x3E00000
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},
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{
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.name = "persistent",
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.offset = 0x4000000,
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.size = 0x4000000
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},
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{
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.name = "persistent1",
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.offset = 0x8000000,
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.size = 0x4000000
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},
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{
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.name = "persistent2",
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.offset = 0xC000000,
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.size = 0x4000000
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}
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};
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struct ndfc_controller_settings warp_ndfc_settings = {
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.ccr_settings = (NDFC_CCR_BS(CS_NAND_0) | NDFC_CCR_ARAC1),
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.ndfc_erpn = 0,
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};
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static struct ndfc_chip_settings warp_chip0_settings = {
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.bank_settings = 0x80002222,
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};
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struct platform_nand_ctrl warp_nand_ctrl = {
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.priv = &warp_ndfc_settings,
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};
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static struct platform_device warp_ndfc_device = {
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.name = "ndfc-nand",
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.id = 0,
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.dev = {
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.platform_data = &warp_nand_ctrl,
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},
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.num_resources = 1,
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.resource = &warp_ndfc,
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};
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/* Do NOT set the ecclayout: let it default so it is correct for both
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* 64M and 256M flash chips.
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*/
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static struct platform_nand_chip warp_nand_chip0 = {
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.nr_chips = 1,
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.chip_offset = CS_NAND_0,
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.nr_partitions = ARRAY_SIZE(nand_parts),
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.partitions = nand_parts,
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.chip_delay = 20,
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.priv = &warp_chip0_settings,
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};
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static struct platform_device warp_nand_device = {
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.name = "ndfc-chip",
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.id = 0,
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.num_resources = 0,
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.dev = {
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.platform_data = &warp_nand_chip0,
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.parent = &warp_ndfc_device.dev,
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}
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};
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static int warp_setup_nand_flash(void)
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{
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struct device_node *np;
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/* Try to detect a rev A based on NOR size. */
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np = of_find_compatible_node(NULL, NULL, "cfi-flash");
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if (np) {
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struct property *pp;
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pp = of_find_property(np, "reg", NULL);
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if (pp && (pp->length == 12)) {
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u32 *v = pp->value;
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if (v[2] == 0x4000000) {
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/* Rev A = 64M NAND */
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warp_nand_chip0.nr_partitions = 3;
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nand_parts[1].size = 0x3000000;
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nand_parts[2].offset = 0x3200000;
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nand_parts[2].size = 0x0e00000;
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}
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}
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of_node_put(np);
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}
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platform_device_register(&warp_ndfc_device);
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platform_device_register(&warp_nand_device);
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return 0;
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}
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machine_device_initcall(warp, warp_setup_nand_flash);
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#endif
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