nvidiafb: access CRT registers safely
Use Read/WriteCrtc() to access CRTC registers in nv_i2c.c. These are safer because it uses the correct CRTC base (0x3bx or 0x3dx). Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -30,16 +30,14 @@ static void nvidia_gpio_setscl(void *data, int state)
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struct nvidia_par *par = chan->par;
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u32 val;
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VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
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val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0;
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val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
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if (state)
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val |= 0x20;
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else
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val &= ~0x20;
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VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
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VGA_WR08(par->PCIO, 0x3d5, val | 0x1);
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NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
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}
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static void nvidia_gpio_setsda(void *data, int state)
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@ -48,16 +46,14 @@ static void nvidia_gpio_setsda(void *data, int state)
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struct nvidia_par *par = chan->par;
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u32 val;
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VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
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val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0;
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val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
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if (state)
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val |= 0x10;
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else
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val &= ~0x10;
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VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
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VGA_WR08(par->PCIO, 0x3d5, val | 0x1);
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NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
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}
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static int nvidia_gpio_getscl(void *data)
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@ -66,8 +62,7 @@ static int nvidia_gpio_getscl(void *data)
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struct nvidia_par *par = chan->par;
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u32 val = 0;
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VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base);
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if (VGA_RD08(par->PCIO, 0x3d5) & 0x04)
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if (NVReadCrtc(par, chan->ddc_base) & 0x04)
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val = 1;
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return val;
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@ -79,8 +74,7 @@ static int nvidia_gpio_getsda(void *data)
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struct nvidia_par *par = chan->par;
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u32 val = 0;
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VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base);
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if (VGA_RD08(par->PCIO, 0x3d5) & 0x08)
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if (NVReadCrtc(par, chan->ddc_base) & 0x08)
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val = 1;
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return val;
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