Merge branch 'upstream/analogix-dp-20160705' of git://github.com/yakir-Yang/linux into drm-next
Please consider merging this tag, which contains the v4 misc fixes and add RK3399 eDP support patches[0] I sent on 2016-06-29, rebased onto v4.7-rc5. * 'upstream/analogix-dp-20160705' of git://github.com/yakir-Yang/linux: dt-bindings: analogix_dp: rockchip: correct the wrong compatible name drm/rockchip: analogix_dp: introduce the pclk for grf drm/bridge: analogix_dp: fix no drm hpd event when panel plug in drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode drm/rockchip: analogix_dp: correct the connector display color format and bpc drm/bridge: analogix_dp: passing the connector as an argument in .get_modes() drm/rockchip: analogix_dp: make panel detect to an optional action drm/rockchip: analogix_dp: add rk3399 eDP support drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 drm/rockchip: analogix_dp: split the lcdc select setting into device data
This commit is contained in:
Dave Airlie
commit
e2b80bac21
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@ -5,6 +5,7 @@ Required properties for dp-controller:
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platform specific such as:
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* "samsung,exynos5-dp"
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* "rockchip,rk3288-dp"
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* "rockchip,rk3399-edp"
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-reg:
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physical base address of the controller and length
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of memory mapped region.
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@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display Port
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================================
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Required properties:
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- compatible: "rockchip,rk3288-edp";
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- compatible: "rockchip,rk3288-dp",
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"rockchip,rk3399-edp";
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- reg: physical base address of the controller and length
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@ -27,6 +28,12 @@ Required properties:
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Port 0: contained 2 endpoints, connecting to the output of vop.
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Port 1: contained 1 endpoint, connecting to the input of panel.
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Optional property for different chips:
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- clocks: from common clock binding: handle to grf_vio clock.
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- clock-names: from common clock binding:
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Required elements: "grf"
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For the below properties, please refer to Analogix DP binding document:
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* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
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- phys (required)
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@ -938,7 +938,7 @@ int analogix_dp_get_modes(struct drm_connector *connector)
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num_modes += drm_panel_get_modes(dp->plat_data->panel);
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if (dp->plat_data->get_modes)
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num_modes += dp->plat_data->get_modes(dp->plat_data);
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num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
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return num_modes;
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}
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@ -1208,6 +1208,7 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
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switch (dp->plat_data->dev_type) {
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case RK3288_DP:
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case RK3399_EDP:
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/*
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* Like Rk3288 DisplayPort TRM indicate that "Main link
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* containing 4 physical lanes of 2.7/1.62 Gbps/lane".
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@ -127,10 +127,10 @@ enum analog_power_block {
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};
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enum dp_irq_type {
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DP_IRQ_TYPE_HP_CABLE_IN,
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DP_IRQ_TYPE_HP_CABLE_OUT,
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DP_IRQ_TYPE_HP_CHANGE,
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DP_IRQ_TYPE_UNKNOWN,
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DP_IRQ_TYPE_HP_CABLE_IN = BIT(0),
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DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1),
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DP_IRQ_TYPE_HP_CHANGE = BIT(2),
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DP_IRQ_TYPE_UNKNOWN = BIT(3),
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};
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struct video_info {
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@ -74,8 +74,12 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
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reg = SEL_24M | TX_DVDD_BIT_1_0625V;
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writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
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if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
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writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
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if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
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reg = REF_CLK_24M;
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if (dp->plat_data->dev_type == RK3288_DP)
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reg ^= REF_CLK_MASK;
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writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
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writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
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writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
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writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
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@ -244,7 +248,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
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u32 reg;
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u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
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if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
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if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
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phy_pd_addr = ANALOGIX_DP_PD;
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switch (block) {
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@ -448,7 +452,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
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analogix_dp_reset_aux(dp);
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/* Disable AUX transaction H/W retry */
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if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
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if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
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reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
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AUX_HW_RETRY_COUNT_SEL(3) |
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AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
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@ -163,8 +163,9 @@
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#define HSYNC_POLARITY_CFG (0x1 << 0)
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/* ANALOGIX_DP_PLL_REG_1 */
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#define REF_CLK_24M (0x1 << 1)
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#define REF_CLK_27M (0x0 << 1)
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#define REF_CLK_24M (0x1 << 0)
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#define REF_CLK_27M (0x0 << 0)
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#define REF_CLK_MASK (0x1 << 0)
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/* ANALOGIX_DP_LANE_MAP */
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#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
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@ -67,10 +67,10 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
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return exynos_dp_crtc_clock_enable(plat_data, false);
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}
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static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data)
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static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
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struct drm_connector *connector)
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{
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struct exynos_dp_device *dp = to_dp(plat_data);
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struct drm_connector *connector = dp->connector;
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struct drm_display_mode *mode;
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int num_modes = 0;
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@ -14,6 +14,7 @@
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#include <linux/component.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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@ -33,13 +34,28 @@
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#include "rockchip_drm_drv.h"
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#include "rockchip_drm_vop.h"
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#define RK3288_GRF_SOC_CON6 0x25c
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#define RK3288_EDP_LCDC_SEL BIT(5)
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#define RK3399_GRF_SOC_CON20 0x6250
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#define RK3399_EDP_LCDC_SEL BIT(5)
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#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
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#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
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/* dp grf register offset */
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#define GRF_SOC_CON6 0x025c
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#define GRF_EDP_LCD_SEL_MASK BIT(5)
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#define GRF_EDP_SEL_VOP_LIT BIT(5)
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#define GRF_EDP_SEL_VOP_BIG 0
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/**
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* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
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* @lcdsel_grf_reg: grf register offset of lcdc select
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* @lcdsel_big: reg value of selecting vop big for eDP
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* @lcdsel_lit: reg value of selecting vop little for eDP
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* @chip_type: specific chip type
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*/
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struct rockchip_dp_chip_data {
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u32 lcdsel_grf_reg;
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u32 lcdsel_big;
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u32 lcdsel_lit;
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u32 chip_type;
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};
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struct rockchip_dp_device {
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struct drm_device *drm_dev;
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@ -48,9 +64,12 @@ struct rockchip_dp_device {
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struct drm_display_mode mode;
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struct clk *pclk;
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struct clk *grfclk;
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struct regmap *grf;
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struct reset_control *rst;
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const struct rockchip_dp_chip_data *data;
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struct analogix_dp_plat_data plat_data;
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};
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@ -92,6 +111,23 @@ static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
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return 0;
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}
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static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
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struct drm_connector *connector)
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{
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struct drm_display_info *di = &connector->display_info;
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/* VOP couldn't output YUV video format for eDP rightly */
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u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
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if ((di->color_formats & mask)) {
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DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
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di->color_formats &= ~mask;
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di->color_formats |= DRM_COLOR_FORMAT_RGB444;
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di->bpc = 8;
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}
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return 0;
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}
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static bool
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rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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@ -119,17 +155,23 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
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return;
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if (ret)
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val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
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val = dp->data->lcdsel_lit;
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else
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val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
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val = dp->data->lcdsel_big;
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dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
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ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
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if (ret != 0) {
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dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
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ret = clk_prepare_enable(dp->grfclk);
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if (ret < 0) {
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dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
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return;
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}
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ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
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if (ret != 0)
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dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
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clk_disable_unprepare(dp->grfclk);
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}
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static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
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@ -143,22 +185,29 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_connector_state *conn_state)
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{
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struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
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struct rockchip_dp_device *dp = to_dp(encoder);
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int ret;
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/*
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* FIXME(Yakir): driver should configure the CRTC output video
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* mode with the display information which indicated the monitor
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* support colorimetry.
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*
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* But don't know why the CRTC driver seems could only output the
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* RGBaaa rightly. For example, if connect the "innolux,n116bge"
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* eDP screen, EDID would indicated that screen only accepted the
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* 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
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* screen would show a blue picture (RGB888 show a green picture).
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* But if I configure CTRC to RGBaaa, and eDP driver still keep
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* RGB666 input video mode, then screen would works prefect.
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* The hardware IC designed that VOP must output the RGB10 video
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* format to eDP controller, and if eDP panel only support RGB8,
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* then eDP controller should cut down the video data, not via VOP
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* controller, that's why we need to hardcode the VOP output mode
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* to RGA10 here.
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*/
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s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
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s->output_type = DRM_MODE_CONNECTOR_eDP;
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if (dp->data->chip_type == RK3399_EDP) {
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/*
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* For RK3399, VOP Lit must code the out mode to RGB888,
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* VOP Big must code the out mode to RGB10.
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*/
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ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
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encoder);
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if (ret > 0)
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s->output_mode = ROCKCHIP_OUT_MODE_P888;
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}
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return 0;
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}
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@ -192,6 +241,16 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp)
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return PTR_ERR(dp->grf);
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}
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dp->grfclk = devm_clk_get(dev, "grf");
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if (PTR_ERR(dp->grfclk) == -ENOENT) {
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dp->grfclk = NULL;
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} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else if (IS_ERR(dp->grfclk)) {
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dev_err(dev, "failed to get grf clock\n");
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return PTR_ERR(dp->grfclk);
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}
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dp->pclk = devm_clk_get(dev, "pclk");
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if (IS_ERR(dp->pclk)) {
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dev_err(dev, "failed to get pclk property\n");
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@ -246,6 +305,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct rockchip_dp_device *dp = dev_get_drvdata(dev);
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const struct rockchip_dp_chip_data *dp_data;
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struct drm_device *drm_dev = data;
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int ret;
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@ -256,10 +316,15 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
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*/
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dev_set_drvdata(dev, NULL);
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dp_data = of_device_get_match_data(dev);
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if (!dp_data)
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return -ENODEV;
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ret = rockchip_dp_init(dp);
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if (ret < 0)
|
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return ret;
|
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|
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dp->data = dp_data;
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dp->drm_dev = drm_dev;
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ret = rockchip_dp_drm_create_encoder(dp);
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@ -270,9 +335,10 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
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dp->plat_data.encoder = &dp->encoder;
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dp->plat_data.dev_type = RK3288_DP;
|
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dp->plat_data.dev_type = dp->data->chip_type;
|
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dp->plat_data.power_on = rockchip_dp_poweron;
|
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dp->plat_data.power_off = rockchip_dp_powerdown;
|
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dp->plat_data.get_modes = rockchip_dp_get_modes;
|
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return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
|
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}
|
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|
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@ -292,38 +358,33 @@ static int rockchip_dp_probe(struct platform_device *pdev)
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{
|
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struct device *dev = &pdev->dev;
|
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struct device_node *panel_node, *port, *endpoint;
|
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struct drm_panel *panel = NULL;
|
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struct rockchip_dp_device *dp;
|
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struct drm_panel *panel;
|
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|
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port = of_graph_get_port_by_id(dev->of_node, 1);
|
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if (!port) {
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dev_err(dev, "can't find output port\n");
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return -EINVAL;
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}
|
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if (port) {
|
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endpoint = of_get_child_by_name(port, "endpoint");
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of_node_put(port);
|
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if (!endpoint) {
|
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dev_err(dev, "no output endpoint found\n");
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return -EINVAL;
|
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}
|
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|
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endpoint = of_get_child_by_name(port, "endpoint");
|
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of_node_put(port);
|
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if (!endpoint) {
|
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dev_err(dev, "no output endpoint found\n");
|
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return -EINVAL;
|
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}
|
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panel_node = of_graph_get_remote_port_parent(endpoint);
|
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of_node_put(endpoint);
|
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if (!panel_node) {
|
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dev_err(dev, "no output node found\n");
|
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return -EINVAL;
|
||||
}
|
||||
|
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panel_node = of_graph_get_remote_port_parent(endpoint);
|
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of_node_put(endpoint);
|
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if (!panel_node) {
|
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dev_err(dev, "no output node found\n");
|
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return -EINVAL;
|
||||
}
|
||||
|
||||
panel = of_drm_find_panel(panel_node);
|
||||
if (!panel) {
|
||||
DRM_ERROR("failed to find panel\n");
|
||||
panel = of_drm_find_panel(panel_node);
|
||||
of_node_put(panel_node);
|
||||
return -EPROBE_DEFER;
|
||||
if (!panel) {
|
||||
DRM_ERROR("failed to find panel\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
}
|
||||
|
||||
of_node_put(panel_node);
|
||||
|
||||
dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
|
||||
if (!dp)
|
||||
return -ENOMEM;
|
||||
|
|
@ -356,8 +417,23 @@ static const struct dev_pm_ops rockchip_dp_pm_ops = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static const struct rockchip_dp_chip_data rk3399_edp = {
|
||||
.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
|
||||
.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
|
||||
.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
|
||||
.chip_type = RK3399_EDP,
|
||||
};
|
||||
|
||||
static const struct rockchip_dp_chip_data rk3288_dp = {
|
||||
.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
|
||||
.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
|
||||
.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
|
||||
.chip_type = RK3288_DP,
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_dp_dt_ids[] = {
|
||||
{.compatible = "rockchip,rk3288-dp",},
|
||||
{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
|
||||
{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
|
||||
|
|
|
|||
|
|
@ -16,8 +16,14 @@
|
|||
enum analogix_dp_devtype {
|
||||
EXYNOS_DP,
|
||||
RK3288_DP,
|
||||
RK3399_EDP,
|
||||
};
|
||||
|
||||
static inline bool is_rockchip(enum analogix_dp_devtype type)
|
||||
{
|
||||
return type == RK3288_DP || type == RK3399_EDP;
|
||||
}
|
||||
|
||||
struct analogix_dp_plat_data {
|
||||
enum analogix_dp_devtype dev_type;
|
||||
struct drm_panel *panel;
|
||||
|
|
@ -28,7 +34,8 @@ struct analogix_dp_plat_data {
|
|||
int (*power_off)(struct analogix_dp_plat_data *);
|
||||
int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *,
|
||||
struct drm_connector *);
|
||||
int (*get_modes)(struct analogix_dp_plat_data *);
|
||||
int (*get_modes)(struct analogix_dp_plat_data *,
|
||||
struct drm_connector *);
|
||||
};
|
||||
|
||||
int analogix_dp_resume(struct device *dev);
|
||||
|
|
|
|||
Loading…
Reference in a new issue