Merge branch 'drm-fixes-4.0' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Some additional radeon fixes for 4.0 * 'drm-fixes-4.0' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: drop setting UPLL to sleep mode drm/radeon: fix wait to actually occur after the signaling callback
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e2cdcafa8a
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@ -1030,37 +1030,59 @@ static inline bool radeon_test_signaled(struct radeon_fence *fence)
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return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
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}
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struct radeon_wait_cb {
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struct fence_cb base;
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struct task_struct *task;
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};
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static void
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radeon_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
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{
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struct radeon_wait_cb *wait =
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container_of(cb, struct radeon_wait_cb, base);
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wake_up_process(wait->task);
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}
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static signed long radeon_fence_default_wait(struct fence *f, bool intr,
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signed long t)
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{
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struct radeon_fence *fence = to_radeon_fence(f);
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struct radeon_device *rdev = fence->rdev;
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bool signaled;
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struct radeon_wait_cb cb;
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fence_enable_sw_signaling(&fence->base);
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cb.task = current;
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/*
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* This function has to return -EDEADLK, but cannot hold
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* exclusive_lock during the wait because some callers
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* may already hold it. This means checking needs_reset without
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* lock, and not fiddling with any gpu internals.
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*
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* The callback installed with fence_enable_sw_signaling will
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* run before our wait_event_*timeout call, so we will see
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* both the signaled fence and the changes to needs_reset.
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*/
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if (fence_add_callback(f, &cb.base, radeon_fence_wait_cb))
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return t;
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if (intr)
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t = wait_event_interruptible_timeout(rdev->fence_queue,
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((signaled = radeon_test_signaled(fence)) ||
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rdev->needs_reset), t);
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else
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t = wait_event_timeout(rdev->fence_queue,
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((signaled = radeon_test_signaled(fence)) ||
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rdev->needs_reset), t);
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while (t > 0) {
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if (intr)
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set_current_state(TASK_INTERRUPTIBLE);
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else
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set_current_state(TASK_UNINTERRUPTIBLE);
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/*
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* radeon_test_signaled must be called after
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* set_current_state to prevent a race with wake_up_process
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*/
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if (radeon_test_signaled(fence))
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break;
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if (rdev->needs_reset) {
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t = -EDEADLK;
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break;
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}
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t = schedule_timeout(t);
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if (t > 0 && intr && signal_pending(current))
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t = -ERESTARTSYS;
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}
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__set_current_state(TASK_RUNNING);
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fence_remove_callback(f, &cb.base);
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if (t > 0 && !signaled)
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return -EDEADLK;
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return t;
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}
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@ -7130,8 +7130,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
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if (!vclk || !dclk) {
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/* keep the Bypass mode, put PLL to sleep */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
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/* keep the Bypass mode */
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return 0;
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}
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@ -7147,8 +7146,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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/* set VCO_MODE to 1 */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
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/* toggle UPLL_SLEEP to 1 then back to 0 */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
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/* disable sleep mode */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
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/* deassert UPLL_RESET */
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